181 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do {    \  argument
187     tcg_gen_extr_i64_i32(rl, rh, ret);                       \
190 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do {        \  argument
194     tcg_gen_extr_i64_i32(rl, rh, ret);                      \
228 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)  in gen_st_2regs_64()  argument
232     tcg_gen_concat_i32_i64(temp, rl, rh);  in gen_st_2regs_64()
236 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,  in gen_offset_st_2regs()  argument
241     gen_st_2regs_64(rh, rl, temp, ctx);  in gen_offset_st_2regs()
244 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)  in gen_ld_2regs_64()  argument
250     tcg_gen_extr_i64_i32(rl, rh, temp);  in gen_ld_2regs_64()
253 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,  in gen_offset_ld_2regs()  argument
258     gen_ld_2regs_64(rh, rl, temp, ctx);  in gen_offset_ld_2regs()
1069 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,  in gen_m16add64_q()  argument
1092     tcg_gen_extr_i64_i32(rl, rh, t3);  in gen_m16add64_q()
1096 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,  in gen_m16adds64_q()  argument
1118     tcg_gen_extr_i64_i32(rl, rh, t1);  in gen_m16adds64_q()
1122 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,  in gen_madd64_q()  argument
1159     tcg_gen_extr_i64_i32(rl, rh, t4);  in gen_madd64_q()
1163     tcg_gen_add_tl(cpu_PSW_AV, rh, rh);  in gen_madd64_q()
1164     tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);  in gen_madd64_q()
1188 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,  in gen_madds64_q()  argument
1196     tcg_gen_extr_i64_i32(rl, rh, r1);  in gen_madds64_q()
1798 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,  in gen_m16sub64_q()  argument
1821     tcg_gen_extr_i64_i32(rl, rh, t3);  in gen_m16sub64_q()
1825 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,  in gen_m16subs64_q()  argument
1847     tcg_gen_extr_i64_i32(rl, rh, t1);  in gen_m16subs64_q()
1851 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,  in gen_msub64_q()  argument
1888     tcg_gen_extr_i64_i32(rl, rh, t4);  in gen_msub64_q()
1892     tcg_gen_add_tl(cpu_PSW_AV, rh, rh);  in gen_msub64_q()
1893     tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);  in gen_msub64_q()
1922 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,  in gen_msubs64_q()  argument
1930     tcg_gen_extr_i64_i32(rl, rh, r1);  in gen_msubs64_q()
2259 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)  in gen_mul_q()  argument
2266             tcg_gen_muls2_tl(rh, rl, arg1, arg2);  in gen_mul_q()
2273             tcg_gen_extr_i64_i32(rl, rh, temp_64);  in gen_mul_q()
2275             tcg_gen_muls2_tl(rl, rh, arg1, arg2);  in gen_mul_q()
2290         tcg_gen_extr_i64_i32(rl, rh, temp_64);  in gen_mul_q()
2293             tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh,  in gen_mul_q()
2305         tcg_gen_add_tl(cpu_PSW_AV, rh, rh);  in gen_mul_q()
2306         tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);  in gen_mul_q()
2742 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)  in gen_bsplit()  argument
2747     tcg_gen_extr_i64_i32(rl, rh, temp);  in gen_bsplit()
2750 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1)  in gen_unpack()  argument
2755     tcg_gen_extr_i64_i32(rl, rh, temp);  in gen_unpack()
2759 gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)  in gen_dvinit_b()  argument
2768     tcg_gen_extr_i64_i32(rl, rh, ret);  in gen_dvinit_b()
2772 gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)  in gen_dvinit_h()  argument
2781     tcg_gen_extr_i64_i32(rl, rh, ret);  in gen_dvinit_h()