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Searched refs:pte (Results 1 – 25 of 26) sorted by relevance

12

/qemu/target/i386/hvf/
H A Dx86_mmu.c27 #define pte_present(pte) (pte & PT_PRESENT) argument
28 #define pte_write_access(pte) (pte & PT_WRITE) argument
29 #define pte_user_access(pte) (pte & PT_USER) argument
30 #define pte_exec_access(pte) (!(pte & PT_NX)) argument
32 #define pte_large_page(pte) (pte & PT_PS) argument
33 #define pte_global_access(pte) (pte & PT_GLOBAL) argument
47 uint64_t pte[5]; member
81 uint64_t pte = 0; in get_pt_entry() local
83 uint64_t gpa = pt->pte[level] & page_mask; in get_pt_entry()
86 gpa = pt->pte[level]; in get_pt_entry()
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/qemu/target/i386/tcg/system/
H A Dexcp_helper.c151 uint64_t ptep, pte, rsvd_mask; in mmu_translate() local
182 pte = ptw_ldq(&pte_trans, ra); in mmu_translate()
183 if (!(pte & PG_PRESENT_MASK)) { in mmu_translate()
186 if (pte & (rsvd_mask | PG_PSE_MASK)) { in mmu_translate()
189 if (!ptw_setl(&pte_trans, pte, PG_ACCESSED_MASK)) { in mmu_translate()
192 ptep = pte ^ PG_NX_MASK; in mmu_translate()
194 pte = in->cr3; in mmu_translate()
201 pte_addr = (pte & PG_ADDRESS_MASK) + (((addr >> 39) & 0x1ff) << 3); in mmu_translate()
206 pte = ptw_ldq(&pte_trans, ra); in mmu_translate()
207 if (!(pte & PG_PRESENT_MASK)) { in mmu_translate()
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/qemu/hw/arm/
H A Dsmmu-internal.h40 #define PTE_ADDRESS(pte, shift) \ argument
41 (extract64(pte, shift, 47 - shift + 1) << shift)
43 #define is_invalid_pte(pte) (!(pte & ARM_LPAE_PTE_VALID)) argument
45 #define is_reserved_pte(pte, level) \ argument
47 ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_L3_PTE_TYPE_RESERVED))
49 #define is_block_pte(pte, level) \ argument
51 ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_BLOCK))
53 #define is_table_pte(pte, level) \ argument
55 ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_TABLE))
57 #define is_page_pte(pte, level) \ argument
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H A Dsmmu-common.c334 static int get_pte(dma_addr_t baseaddr, uint32_t index, uint64_t *pte, in get_pte() argument
338 dma_addr_t addr = baseaddr + index * sizeof(*pte); in get_pte()
341 ret = ldq_le_dma(&address_space_memory, addr, pte, MEMTXATTRS_UNSPECIFIED); in get_pte()
348 trace_smmu_get_pte(baseaddr, index, addr, *pte); in get_pte()
359 static inline hwaddr get_page_pte_address(uint64_t pte, int granule_sz) in get_page_pte_address() argument
361 return PTE_ADDRESS(pte, granule_sz); in get_page_pte_address()
369 static inline hwaddr get_table_pte_address(uint64_t pte, int granule_sz) in get_table_pte_address() argument
371 return PTE_ADDRESS(pte, granule_sz); in get_table_pte_address()
378 static inline hwaddr get_block_pte_address(uint64_t pte, int level, in get_block_pte_address() argument
384 return PTE_ADDRESS(pte, n); in get_block_pte_address()
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H A Dtrace-events15 …r, uint32_t offset, uint64_t pte) "stage=%d level=%d iova=0x%"PRIx64" subpage_sz=0x%zx baseaddr=0x…
16 …64_t pteaddr, uint32_t offset, uint64_t pte) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64"…
17 … uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=%d level=%d iova=0x%"PRIx64" base@=0x%"P…
18 …t64_t pteaddr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=%d level=%d base@=0…
19 …eaddr, int index, uint64_t pteaddr, uint64_t pte) "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PR…
/qemu/target/i386/
H A Dmonitor.c52 hwaddr pte, hwaddr mask) in print_pte() argument
59 pte & mask, in print_pte()
60 pte & PG_NX_MASK ? 'X' : '-', in print_pte()
61 pte & PG_GLOBAL_MASK ? 'G' : '-', in print_pte()
62 pte & PG_PSE_MASK ? 'P' : '-', in print_pte()
63 pte & PG_DIRTY_MASK ? 'D' : '-', in print_pte()
64 pte & PG_ACCESSED_MASK ? 'A' : '-', in print_pte()
65 pte & PG_PCD_MASK ? 'C' : '-', in print_pte()
66 pte & PG_PWT_MASK ? 'T' : '-', in print_pte()
67 pte & PG_USER_MASK ? 'U' : '-', in print_pte()
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H A Darch_memory_mapping.c25 uint64_t pte; in walk_pte() local
31 pte = address_space_ldq(as, pte_addr, MEMTXATTRS_UNSPECIFIED, NULL); in walk_pte()
32 if (!(pte & PG_PRESENT_MASK)) { in walk_pte()
37 start_paddr = (pte & ~0xfff) & ~(0x1ULL << 63); in walk_pte()
55 uint32_t pte; in walk_pte2() local
61 pte = address_space_ldl(as, pte_addr, MEMTXATTRS_UNSPECIFIED, NULL); in walk_pte2()
62 if (!(pte & PG_PRESENT_MASK)) { in walk_pte2()
67 start_paddr = pte & ~0xfff; in walk_pte2()
H A Dhelper.c247 uint64_t pte; in x86_cpu_get_phys_page_attrs_debug() local
256 pte = addr & a20_mask; in x86_cpu_get_phys_page_attrs_debug()
300 pte = pdpe; in x86_cpu_get_phys_page_attrs_debug()
323 pte = pde; in x86_cpu_get_phys_page_attrs_debug()
329 pte = x86_ldq_phys(cs, pte_addr); in x86_cpu_get_phys_page_attrs_debug()
331 if (!(pte & PG_PRESENT_MASK)) { in x86_cpu_get_phys_page_attrs_debug()
343 pte = pde | ((pde & 0x1fe000LL) << (32 - 13)); in x86_cpu_get_phys_page_attrs_debug()
348 pte = x86_ldl_phys(cs, pte_addr); in x86_cpu_get_phys_page_attrs_debug()
349 if (!(pte & PG_PRESENT_MASK)) { in x86_cpu_get_phys_page_attrs_debug()
354 pte = pte & a20_mask; in x86_cpu_get_phys_page_attrs_debug()
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/qemu/target/ppc/
H A Dmmu-radix64.c215 static int ppc_radix64_get_prot_eaa(uint64_t pte) in ppc_radix64_get_prot_eaa() argument
217 return (pte & R_PTE_EAA_R ? PAGE_READ : 0) | in ppc_radix64_get_prot_eaa()
218 (pte & R_PTE_EAA_RW ? PAGE_READ | PAGE_WRITE : 0) | in ppc_radix64_get_prot_eaa()
219 (pte & R_PTE_EAA_X ? PAGE_EXEC : 0); in ppc_radix64_get_prot_eaa()
234 uint64_t pte, int *fault_cause, int *prot, in ppc_radix64_check_prot() argument
240 if ((pte & R_PTE_ATT) == R_PTE_ATT_NI_IO && access_type == MMU_INST_FETCH) { in ppc_radix64_check_prot()
250 if (!partition_scoped && (pte & R_PTE_EAA_PRIV) && in ppc_radix64_check_prot()
253 } else if (mmuidx_pr(mmu_idx) || (pte & R_PTE_EAA_PRIV) || in ppc_radix64_check_prot()
255 *prot = ppc_radix64_get_prot_eaa(pte); in ppc_radix64_check_prot()
257 *prot = ppc_radix64_get_prot_eaa(pte); in ppc_radix64_check_prot()
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H A Dmmu-hash32.c206 ppc_hash_pte32_t *pte) in ppc_hash32_pteg_search() argument
225 pte->pte0 = pte0; in ppc_hash32_pteg_search()
226 pte->pte1 = pte1; in ppc_hash32_pteg_search()
256 ppc_hash_pte32_t *pte) in ppc_hash32_htab_lookup() argument
280 pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 0, ptem, pte); in ppc_hash32_htab_lookup()
288 pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 1, ptem, pte); in ppc_hash32_htab_lookup()
302 ppc_hash_pte32_t pte; in ppc_hash32_xlate() local
363 pte_offset = ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte); in ppc_hash32_xlate()
387 prot = ppc_hash32_prot(key, pte.pte1 & HPTE32_R_PP, sr & SR32_NX); in ppc_hash32_xlate()
414 if (!(pte.pte1 & HPTE32_R_R)) { in ppc_hash32_xlate()
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H A Dmmu-hash64.c390 ppc_hash_pte64_t pte) in ppc_hash64_pte_noexec_guard() argument
393 return (pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G) ? in ppc_hash64_pte_noexec_guard()
399 ppc_slb_t *slb, ppc_hash_pte64_t pte) in ppc_hash64_pte_prot() argument
410 pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61); in ppc_hash64_pte_prot()
462 static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte) in ppc_hash64_amr_prot() argument
473 key = HPTE64_R_KEY(pte.pte1); in ppc_hash64_amr_prot()
650 ppc_hash_pte64_t *pte, unsigned *pshift) in ppc_hash64_pteg_search() argument
694 pte->pte0 = pte0; in ppc_hash64_pteg_search()
695 pte->pte1 = pte1; in ppc_hash64_pteg_search()
709 ppc_hash_pte64_t *pte, unsigned *pshift) in ppc_hash64_htab_lookup() argument
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/qemu/hw/sparc/
H A Dsun4m_iommu.c264 uint32_t pte) in iommu_translate_pa() argument
268 pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK); in iommu_translate_pa()
269 trace_sun4m_iommu_translate_pa(addr, pa, pte); in iommu_translate_pa()
295 uint32_t pte; in sun4m_translate_iommu() local
305 pte = iommu_page_get_flags(is, page); in sun4m_translate_iommu()
306 if (!(pte & IOPTE_VALID)) { in sun4m_translate_iommu()
311 pa = iommu_translate_pa(addr, pte); in sun4m_translate_iommu()
312 if (is_write && !(pte & IOPTE_WRITE)) { in sun4m_translate_iommu()
317 if (pte & IOPTE_WRITE) { in sun4m_translate_iommu()
H A Dtrace-events13 …64_t pa, uint64_t iopte, uint32_t ret) "get flags addr 0x%"PRIx64" => pte 0x%"PRIx64", *pte = 0x%x"
/qemu/target/riscv/
H A Dcpu_helper.c1319 target_ulong pte; in get_physical_address() local
1367 pte = address_space_ldl(cs->as, pte_addr, attrs, &res); in get_physical_address()
1369 pte = address_space_ldq(cs->as, pte_addr, attrs, &res); in get_physical_address()
1377 ppn = pte >> PTE_PPN_SHIFT; in get_physical_address()
1379 if (pte & PTE_RESERVED) { in get_physical_address()
1382 __func__, pte_addr, pte); in get_physical_address()
1386 if (!pbmte && (pte & PTE_PBMT)) { in get_physical_address()
1391 __func__, pte_addr, pte); in get_physical_address()
1395 if (!riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { in get_physical_address()
1400 __func__, pte_addr, pte); in get_physical_address()
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H A Dmonitor.c89 target_ulong pte; in walk_pte() local
103 cpu_physical_memory_read(pte_addr, &pte, ptesize); in walk_pte()
105 paddr = (hwaddr)(pte >> PTE_PPN_SHIFT) << PGSHIFT; in walk_pte()
106 attr = pte & 0xff; in walk_pte()
/qemu/contrib/elf2dmp/
H A Daddrspace.c175 static uint64_t get_paddr(uint64_t va, uint64_t pte) in get_paddr() argument
177 return (pte & 0xFFFFFFFFFF000) | (va & 0xFFF); in get_paddr()
202 uint64_t pml4e, pdpe, pgd, pte; in va_space_va2pa() local
224 if (!get_pte(vs, va, pgd, &pte) || !is_present(pte)) { in va_space_va2pa()
228 return get_paddr(va, pte); in va_space_va2pa()
/qemu/hw/i386/
H A Damd_iommu.c886 static inline uint8_t get_pte_translation_mode(uint64_t pte) in get_pte_translation_mode() argument
888 return (pte >> AMDVI_DEV_MODE_RSHIFT) & AMDVI_DEV_MODE_MASK; in get_pte_translation_mode()
891 static inline uint64_t pte_override_page_mask(uint64_t pte) in pte_override_page_mask() argument
894 uint64_t addr = (pte & AMDVI_DEV_PT_ROOT_MASK) >> 12; in pte_override_page_mask()
912 uint64_t pte; in amdvi_get_pte_entry() local
915 &pte, sizeof(pte), MEMTXATTRS_UNSPECIFIED)) { in amdvi_get_pte_entry()
918 pte = 0; in amdvi_get_pte_entry()
919 return pte; in amdvi_get_pte_entry()
922 pte = le64_to_cpu(pte); in amdvi_get_pte_entry()
923 return pte; in amdvi_get_pte_entry()
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H A Dintel_iommu.c422 uint16_t domain_id, hwaddr addr, uint64_t pte, in vtd_update_iotlb() argument
430 trace_vtd_iotlb_page_update(source_id, addr, pte, domain_id); in vtd_update_iotlb()
438 entry->pte = pte; in vtd_update_iotlb()
756 static inline uint64_t vtd_get_pte_addr(uint64_t pte, uint8_t aw) in vtd_get_pte_addr() argument
758 return pte & VTD_PT_BASE_ADDR_MASK(aw); in vtd_get_pte_addr()
762 static inline bool vtd_is_last_pte(uint64_t pte, uint32_t level) in vtd_is_last_pte() argument
764 return level == VTD_PT_LEVEL || (pte & VTD_PT_PAGE_SIZE_MASK); in vtd_is_last_pte()
770 uint64_t pte; in vtd_get_pte() local
775 base_addr + index * sizeof(pte), in vtd_get_pte()
776 &pte, sizeof(pte), MEMTXATTRS_UNSPECIFIED)) { in vtd_get_pte()
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/qemu/target/xtensa/
H A Dmmu_helper.c282 uint32_t pte) in xtensa_tlb_set_entry_mmu() argument
285 entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi); in xtensa_tlb_set_entry_mmu()
286 entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff; in xtensa_tlb_set_entry_mmu()
287 entry->attr = pte & 0xf; in xtensa_tlb_set_entry_mmu()
292 uint32_t vpn, uint32_t pte) in xtensa_tlb_set_entry() argument
302 xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte); in xtensa_tlb_set_entry()
313 entry->paddr = pte & REGION_PAGE_MASK; in xtensa_tlb_set_entry()
315 entry->attr = pte & 0xf; in xtensa_tlb_set_entry()
805 static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
817 uint32_t pte; in get_physical_addr_mmu() local
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/qemu/hw/riscv/
H A Driscv-iommu.c255 uint64_t satp, gatp, pte; in riscv_iommu_spa_fetch() local
425 pte = pte32; in riscv_iommu_spa_fetch()
427 ret = ldq_le_dma(s->target_as, pte_addr, &pte, in riscv_iommu_spa_fetch()
436 hwaddr ppn = pte >> PTE_PPN_SHIFT; in riscv_iommu_spa_fetch()
438 if (!(pte & PTE_V)) { in riscv_iommu_spa_fetch()
440 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { in riscv_iommu_spa_fetch()
442 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { in riscv_iommu_spa_fetch()
444 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { in riscv_iommu_spa_fetch()
448 } else if ((iotlb->perm & IOMMU_RO) && !(pte & PTE_R)) { in riscv_iommu_spa_fetch()
450 } else if ((iotlb->perm & IOMMU_WO) && !(pte & PTE_W)) { in riscv_iommu_spa_fetch()
[all …]
H A Driscv-iommu-bits.h446 uint64_t pte; member
/qemu/hw/alpha/
H A Dtyphoon.c625 uint64_t pte = address_space_ldq(&address_space_memory, pte_addr, in pte_translate() local
629 if ((pte & 1) == 0) { in pte_translate()
633 return make_iommu_tlbe((pte & 0x3ffffe) << 12, 0x1fff, ret); in pte_translate()
/qemu/include/hw/i386/
H A Dintel_iommu.h156 uint64_t pte; member
/qemu/pc-bios/s390-ccw/
H A Dbootmap.c678 static int zipl_run(ScsiBlockPtr *pte) in zipl_run() argument
684 if (virtio_read(pte->blockno, tmp_sec)) { in zipl_run()
/qemu/target/mips/tcg/system/
H A Dtlb_helper.c597 uint64_t *pte, unsigned ptw_mmu_idx) in get_pte() argument
607 *pte = cpu_ldq_mmu(env, vaddr, oi, 0); in get_pte()
609 *pte = cpu_ldl_mmu(env, vaddr, oi, 0); in get_pte()

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