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Searched refs:pins (Results 1 – 11 of 11) sorted by relevance

/qemu/hw/core/
H A Dgpio.c74 void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins, in qdev_init_gpio_out_named() argument
85 memset(pins, 0, sizeof(*pins) * n); in qdev_init_gpio_out_named()
91 (Object **)&pins[i], in qdev_init_gpio_out_named()
99 void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n) in qdev_init_gpio_out() argument
101 qdev_init_gpio_out_named(dev, pins, NULL, n); in qdev_init_gpio_out()
/qemu/hw/gpio/
H A Domap_gpio.c41 uint16_t pins; member
84 return s->inputs & s->pins; in omap_gpio_read()
103 return s->pins; in omap_gpio_read()
166 s->pins = value; in omap_gpio_write()
190 s->pins = ~0; in omap_gpio_reset()
H A Dtrace-events48 stm32l4x5_gpio_pins(char *gpio, uint16_t disconnected, uint16_t high) "GPIO%s disconnected pins: 0x…
/qemu/rust/qemu-api/src/
H A Dqdev.rs381 fn init_gpio_out(&self, pins: &[InterruptSource]) { in init_gpio_out()
385 InterruptSource::slice_as_ptr(pins), in init_gpio_out()
386 pins.len() as c_int,
/qemu/docs/specs/
H A Daspeed-intc.rst22 from INTCIO and connected to INTC at input pin 0 and output pins 0 to 9 for
33 The design of INTC GIC_192_201 have 10 output pins, mapped as following:
/qemu/include/hw/
H A Dqdev-core.h802 void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n);
815 void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins,
/qemu/pc-bios/dtb/
H A Dbamboo.dts178 /* Bamboo has all 4 IRQ pins tied together per slot */
/qemu/hw/intc/
H A Domap_intc.c44 qemu_irq *pins; member
/qemu/docs/system/devices/
H A Dvhost-user.rst35 - Proxy gpio pins to host
/qemu/docs/system/riscv/
H A Dsifive_u.rst91 Mode Select (MSEL[3:0]) pins value, used to control where to boot from.
94 using the Mode Select pins on the chip. Typically, the boot process runs
/qemu/docs/devel/migration/
H A Dvfio.rst135 perpetually marked dirty, unless the device driver pins pages through external