| /qemu/hw/timer/ |
| H A D | hpet.c | 483 uint64_t old_val, new_val, cleared; in hpet_ram_write() local
494 old_val = s->config; in hpet_ram_write()
495 new_val = deposit64(old_val, shift, len, value); in hpet_ram_write()
496 new_val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); in hpet_ram_write()
498 if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) { in hpet_ram_write()
508 } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) { in hpet_ram_write()
517 if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) { in hpet_ram_write()
521 } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) { in hpet_ram_write()
558 old_val = timer->config; in hpet_ram_write()
559 new_val = deposit64(old_val, shif in hpet_ram_write()
[all...] |
| H A D | exynos4210_mct.c | 1179 uint32_t old_val; in exynos4210_mct_write() local
1247 old_val = s->g_timer.reg.tcon; in exynos4210_mct_write()
1256 if ((value & G_TCON_TIMER_ENABLE) > (old_val & in exynos4210_mct_write()
1260 if ((value & G_TCON_TIMER_ENABLE) < (old_val & in exynos4210_mct_write()
1267 if ((value & G_TCON_COMP_ENABLE(i)) != (old_val & in exynos4210_mct_write()
1319 old_val = s->l_timer[lt_i].reg.tcon; in exynos4210_mct_write()
1327 (old_val & L_TCON_TICK_START)) { in exynos4210_mct_write()
1334 (old_val & L_TCON_INT_START)) { in exynos4210_mct_write()
1341 (old_val & L_TCON_TICK_START)) { in exynos4210_mct_write()
1348 (old_val & L_TCON_INT_START)) { in exynos4210_mct_write()
[all …]
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| /qemu/rust/hw/timer/hpet/src/ |
| H A D | device.rs | 406 let old_val: u64 = self.config; in set_tn_cfg_reg() localVariable
407 let mut new_val: u64 = old_val.deposit(shift, len, val); in set_tn_cfg_reg()
408 new_val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); in set_tn_cfg_reg()
411 if deactivating_bit(old_val, new_val, HPET_TN_CFG_INT_TYPE_SHIFT) { in set_tn_cfg_reg()
419 if activating_bit(old_val, new_val, HPET_TN_CFG_INT_ENABLE_SHIFT) && self.is_int_active() { in set_tn_cfg_reg()
623 let old_val = self.config.get(); in update_int_status()
624 let mut new_val = old_val.deposit(shift, len, val); in update_int_status()
626 new_val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
629 if activating_bit(old_val, new_val, HPET_CFG_ENABLE_SHIFT) { in set_cfg_reg()
642 } else if deactivating_bit(old_val, new_va in set_cfg_reg()
628 let old_val = self.config.get(); set_cfg_reg() localVariable
[all...] |
| /qemu/tests/tcg/hexagon/ |
| H A D | preg_alias.c | 103 uint32_t old_val = 0x0000001c; in test_packet() local
106 result = old_val; in test_packet()
116 check32(result, old_val); in test_packet()
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| H A D | misc.c | 225 static inline int32_t test_clrtnew(int32_t arg1, int32_t old_val) in test_clrtnew() argument
235 : "r"(arg1), "r"(old_val) in test_clrtnew()
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| /qemu/hw/intc/ |
| H A D | riscv_imsic.c | 95 target_ulong old_val = imsic->eidelivery[page]; in riscv_imsic_eidelivery_rmw() local
98 *val = old_val; in riscv_imsic_eidelivery_rmw()
102 imsic->eidelivery[page] = (old_val & ~wr_mask) | (new_val & wr_mask); in riscv_imsic_eidelivery_rmw()
113 target_ulong old_val = imsic->eithreshold[page]; in riscv_imsic_eithreshold_rmw() local
116 *val = old_val; in riscv_imsic_eithreshold_rmw()
120 imsic->eithreshold[page] = (old_val & ~wr_mask) | (new_val & wr_mask); in riscv_imsic_eithreshold_rmw()
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| /qemu/hw/core/ |
| H A D | register.c | 74 uint64_t old_val, new_val, test, no_w_mask; in register_write() local
87 old_val = reg->data ? register_read_val(reg) : ac->reset; in register_write()
89 test = (old_val ^ val) & ac->rsvd; in register_write()
107 new_val = (val & ~no_w_mask) | (old_val & no_w_mask); in register_write()
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| H A D | qdev-properties-system.c | 41 const void *old_val, const char *new_val, in check_prop_still_unset() argument
46 if (!old_val || (!prop && allow_override)) { in check_prop_still_unset()
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| /qemu/tests/tcg/multiarch/gdbstub/ |
| H A D | registers.py | 184 old_val = e["initial"]
192 if new_val != old_val:
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| /qemu/hw/net/ |
| H A D | e1000x_common.c | 331 uint32_t old_val = mac[TIMINCA]; in e1000x_set_timinca() local
332 uint32_t old_incvalue = old_val & E1000_TIMINCA_INCVALUE_MASK; in e1000x_set_timinca()
333 uint32_t old_incperiod = MAX(old_val >> E1000_TIMINCA_INCPERIOD_SHIFT, 1); in e1000x_set_timinca()
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| H A D | opencores_eth.c | 315 uint32_t old_val = s->regs[INT_SOURCE]; in open_eth_int_source_write() local
318 open_eth_update_irq(s, old_val & s->regs[INT_MASK], in open_eth_int_source_write()
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| H A D | tulip.c | 711 static void tulip_csr9_write(TULIPState *s, uint32_t old_val, in tulip_csr9_write() argument
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| /qemu/hw/watchdog/ |
| H A D | allwinner-wdt.c | 237 uint32_t old_val; in allwinner_wdt_write() local
257 old_val = s->regs[REG_MODE]; in allwinner_wdt_write()
261 if ((s->regs[REG_MODE] & ~old_val) & WDT_EN_MASK) { in allwinner_wdt_write()
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| /qemu/target/arm/ |
| H A D | ptw.c | 736 static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, in arm_casq_ptw() argument
766 return old_val; in arm_casq_ptw()
768 if (cur_val == old_val) { in arm_casq_ptw()
776 return old_val; in arm_casq_ptw()
788 return old_val; in arm_casq_ptw()
790 if (cur_val == old_val) { in arm_casq_ptw()
798 return old_val; in arm_casq_ptw()
843 old_val = cpu_to_be64(old_val); in arm_casq_ptw()
845 cur_val = qatomic_cmpxchg__nocheck((uint64_t *)host, old_val, new_val); in arm_casq_ptw()
848 old_val = cpu_to_le64(old_val); in arm_casq_ptw()
[all …]
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| /qemu/include/system/ |
| H A D | memory.h | 910 int old_val, int new_val);
929 int old_val, int new_val);
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| /qemu/target/riscv/ |
| H A D | csr.c | 2470 target_ulong old_val; in rmw_iprio() local
2482 old_val = 0; in rmw_iprio()
2484 old_val |= ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * i); in rmw_iprio()
2488 *val = old_val; in rmw_iprio()
2492 new_val = (old_val & ~wr_mask) | (new_val & wr_mask); in rmw_iprio()
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