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Searched refs:msb (Results 1 – 23 of 23) sorted by relevance

/qemu/tests/fp/
H A Dfp-test-log2.c27 int msb; in compare() local
33 msb = 63 - __builtin_clzll(real.i ^ soft.i); in compare()
35 if (msb < 52) { in compare()
53 if (msb == 63) { in compare()
55 } else if (msb >= 52) { in compare()
/qemu/target/riscv/
H A Dxthead.decode29 &th_bfext msb lsb rs1 rd
39 @th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd
/qemu/tcg/s390x/
H A Dtcg-target.c.inc1138 int msb, int lsb, int ofs, int z)
1142 tcg_out16(s, (msb << 8) | (z << 7) | lsb);
1193 int msb, lsb;
1195 /* Achieve wraparound by swapping msb and lsb. */
1196 msb = 64 - ctz64(~val);
1199 msb = clz64(val);
1202 tcg_out_risbg(s, out, in, msb, lsb, 0, 1);
1586 unsigned msb = lsb - (len - 1);
1599 tcg_out_risbg(s, a0, a2, msb, lsb, ofs, false);
1606 unsigned msb = lsb - (len - 1);
[all …]
/qemu/fpu/
H A Dsoftfloat-specialize.c.inc94 * the msb must be zero. MIPS is (so far) unique in supporting both the
112 bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
113 return msb == snan_bit_is_one(status);
H A Dsoftfloat-parts.c.inc1748 * the msb parts of the fraction. At the end, when we subtract
1777 * are lots of 0's in the msb parts of the fraction.
/qemu/hw/net/
H A Dtulip.c904 unsigned int msb, bit, i; in tulip_srom_crc() local
909 msb = (crc >> 31) & 1; in tulip_srom_crc()
911 if (msb ^ (currentbyte & 1)) { in tulip_srom_crc()
/qemu/target/hexagon/
H A Dmacros.h330 TCGv msb = tcg_temp_new(); in gen_read_ireg() local
334 tcg_gen_sari_tl(msb, val, 21); in gen_read_ireg()
335 tcg_gen_deposit_tl(result, msb, lsb, 0, 7); in gen_read_ireg()
/qemu/tcg/mips/
H A Dtcg-target.c.inc404 TCGReg rs, int msb, int lsb)
411 inst |= (msb & 0x1F) << 11;
418 int msb, int lsb)
422 msb -= 32;
424 } else if (msb >= 32) {
426 msb -= 32;
428 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
1711 int msb;
1720 msb = ctz64(~a2) - 1;
1722 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
[all …]
/qemu/target/arm/tcg/
H A Da32.decode47 &bfi rd rn lsb msb
424 BFCI ---- 0111 110 msb:5 rd:4 lsb:5 001 rn:4 &bfi
H A Dt32.decode44 &bfi !extern rd rn lsb msb
252 @bfi .... .... ... . rn:4 . ... rd:4 .. . msb:5 \
H A Dtranslate.c5694 int msb = a->msb, lsb = a->lsb; in trans_BFCI() local
5701 if (msb < lsb) { in trans_BFCI()
5707 width = msb + 1 - lsb; in trans_BFCI()
/qemu/target/riscv/insn_trans/
H A Dtrans_rvb.c.inc317 /* Set msb in each byte if the byte was non-zero. */
322 /* Extract the msb to the lsb in each byte */
H A Dtrans_xthead.c.inc164 if (a->lsb <= a->msb) {
165 f(dest, source, a->lsb, a->msb - a->lsb + 1);
/qemu/target/openrisc/
H A Ddisas.c112 INSN(msb, "r%d, r%d", a->a, a->b)
/qemu/target/mips/tcg/
H A Ddsp_helper.c2923 uint32_t pos, size, msb, lsb; \
2933 msb = pos + size - 1; \
2936 if (lsb > msb || (msb > TARGET_LONG_BITS)) { \
H A Dtranslate.c4621 int rs, int lsb, int msb) in gen_bitops() argument
4629 if (lsb + msb > 31) { in gen_bitops()
4632 if (msb != 31) { in gen_bitops()
4633 tcg_gen_extract_tl(t0, t1, lsb, msb + 1); in gen_bitops()
4647 msb += 32; in gen_bitops()
4651 if (lsb + msb > 63) { in gen_bitops()
4654 tcg_gen_extract_tl(t0, t1, lsb, msb + 1); in gen_bitops()
4658 if (lsb > msb) { in gen_bitops()
4662 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); in gen_bitops()
4670 msb += 32; in gen_bitops()
[all …]
/qemu/target/ppc/translate/
H A Dvsx-impl.c.inc696 uint64_t msb = (vece == MO_32) ? SGN_MASK_SP : SGN_MASK_DP;
697 tcg_gen_op_vec(vece, t, b, tcg_constant_vec_matching(t, vece, msb));
762 uint64_t msb = (vece == MO_32) ? SGN_MASK_SP : SGN_MASK_DP;
763 tcg_gen_bitsel_vec(vece, t, tcg_constant_vec_matching(t, vece, msb), a, b);
/qemu/disas/
H A Dmips.c4247 unsigned int lsb, msb, msbd; in print_insn_args() local
4280 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB; in print_insn_args()
4281 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); in print_insn_args()
4421 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32; in print_insn_args()
4422 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); in print_insn_args()
H A Dnanomips.c72 static int64 sign_extend(int64 data, int msb) in sign_extend() argument
74 uint64 shift = 63 - msb; in sign_extend()
/qemu/target/hppa/
H A Dtranslate.c3900 uint64_t msb = 1ULL << (len - 1); in do_dep_sar() local
3911 tcg_gen_movi_i64(mask, msb + (msb - 1)); in do_dep_sar()
/qemu/hw/i386/
H A Dintel_iommu.c1956 bool msb = ((iova & (iova_limit >> 1)) != 0); in vtd_iova_fl_check_canonical() local
1958 if (msb) { in vtd_iova_fl_check_canonical()
/qemu/tcg/aarch64/
H A Dtcg-target.c.inc175 /* Make things easier below, by testing the form with msb clear. */
/qemu/target/hexagon/imported/mmvec/
H A Dext.idef1578 "Vector halfword by halfword multiply, shift by 1, and take upper 16 msb",