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Searched refs:mmu (Results 1 – 25 of 34) sorted by relevance

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/qemu/target/microblaze/
H A Dmmu.c42 MicroBlazeMMU *mmu = &env->mmu; in mmu_flush_idx() local
46 t = mmu->rams[RAM_TAG][idx]; in mmu_flush_idx()
62 MicroBlazeMMU *mmu = &env->mmu; in mmu_change_pid() local
69 for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) { in mmu_change_pid()
71 t = mmu->rams[RAM_TAG][i]; in mmu_change_pid()
73 if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i])) in mmu_change_pid()
83 MicroBlazeMMU *mmu = &cpu->env.mmu; in mmu_translate() local
90 for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) { in mmu_translate()
94 t = mmu->rams[RAM_TAG][i]; in mmu_translate()
107 if (mmu->tids[i] in mmu_translate()
[all …]
H A Dmeson.build15 'mmu.c',
H A Dcpu.h287 MicroBlazeMMU mmu; member
315 uint8_t mmu; member
H A Dmmu.h92 void mmu_init(MicroBlazeMMU *mmu);
H A Dmachine.c83 VMSTATE_STRUCT(mmu, CPUMBState, 0, vmstate_mmu, MicroBlazeMMU),
H A Dcpu.c232 mmu_init(&env->mmu); in mb_cpu_reset_hold()
333 cpu->cfg.mmu = 3; in mb_cpu_realizefn()
/qemu/target/m68k/
H A Dhelper.c206 env->mmu.tcr = val; in HELPER()
213 env->mmu.mmusr = val; in HELPER()
221 env->mmu.srp = val; in HELPER()
229 env->mmu.urp = val; in HELPER()
258 env->mmu.ttr[M68K_ITTR0] = val; in HELPER()
265 env->mmu.ttr[M68K_ITTR1] = val; in HELPER()
272 env->mmu.ttr[M68K_DTTR0] = val; in HELPER()
279 env->mmu.ttr[M68K_DTTR1] = val; in HELPER()
321 return env->mmu.tcr; in HELPER()
327 return env->mmu.mmusr; in HELPER()
[all …]
H A Dmonitor.c49 { "urp", offsetof(CPUM68KState, mmu.urp) },
50 { "srp", offsetof(CPUM68KState, mmu.srp) },
51 { "dttr0", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR0]) },
52 { "dttr1", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR1]) },
53 { "ittr0", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR0]) },
54 { "ittr1", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR1]) },
55 { "mmusr", offsetof(CPUM68KState, mmu.mmusr) },
H A Dop_helper.c323 if (env->mmu.fault) { in m68k_interrupt_all()
326 env->mmu.fault = true; in m68k_interrupt_all()
353 cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); in m68k_interrupt_all()
356 cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); in m68k_interrupt_all()
368 cpu_stw_mmuidx_ra(env, sp, env->mmu.ssw, MMU_KERNEL_IDX, 0); in m68k_interrupt_all()
371 cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); in m68k_interrupt_all()
374 env->mmu.fault = false; in m68k_interrupt_all()
378 env->mmu.ssw, env->mmu.ar, env->sfc, env->dfc); in m68k_interrupt_all()
394 do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc); in m68k_interrupt_all()
451 env->mmu.mmusr = 0; in m68k_cpu_transaction_failed()
[all …]
H A Dcpu.c538 VMSTATE_UINT32(env.mmu.ar, M68kCPU),
539 VMSTATE_UINT32(env.mmu.ssw, M68kCPU),
540 VMSTATE_UINT16(env.mmu.tcr, M68kCPU),
541 VMSTATE_UINT32(env.mmu.urp, M68kCPU),
542 VMSTATE_UINT32(env.mmu.srp, M68kCPU),
543 VMSTATE_BOOL(env.mmu.fault, M68kCPU),
544 VMSTATE_UINT32_ARRAY(env.mmu.ttr, M68kCPU, 4),
545 VMSTATE_UINT32(env.mmu.mmusr, M68kCPU),
H A Dcpu.h140 } mmu; member
/qemu/linux-user/riscv/
H A Dtarget_proc.h16 const char *mmu; in open_cpuinfo() local
18 if (cfg->mmu) { in open_cpuinfo()
19 mmu = (cpu_env->xl == MXL_RV32) ? "sv32" : "sv48"; in open_cpuinfo()
21 mmu = "none"; in open_cpuinfo()
28 dprintf(fd, "mmu\t\t: %s\n", mmu); in open_cpuinfo()
/qemu/target/ppc/
H A Dmeson.build40 'mmu-hash32.c',
41 'mmu-booke.c',
54 'mmu-book3s-v3.c',
55 'mmu-hash64.c',
56 'mmu-radix64.c',
/qemu/linux-user/m68k/
H A Dcpu_loop.c46 force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->mmu.ar); in cpu_loop()
49 force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->mmu.ar); in cpu_loop()
52 force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_TRACE, env->mmu.ar); in cpu_loop()
/qemu/target/mips/tcg/system/
H A Dtlb_helper.c56 tlb = &env->tlb->mmu.r4k.tlb[idx]; in r4k_fill_tlb()
95 tlb = &env->tlb->mmu.r4k.tlb[idx]; in r4k_helper_tlbinv()
109 env->tlb->mmu.r4k.tlb[idx].EHINV = 1; in r4k_helper_tlbinvf()
128 tlb = &env->tlb->mmu.r4k.tlb[idx]; in r4k_helper_tlbwi()
184 tlb = &env->tlb->mmu.r4k.tlb[i]; in r4k_helper_tlbp()
203 tlb = &env->tlb->mmu.r4k.tlb[i]; in r4k_helper_tlbp()
244 tlb = &env->tlb->mmu.r4k.tlb[idx]; in r4k_helper_tlbr()
320 tlb = &env->tlb->mmu.r4k.tlb[idx]; in global_invalidate_tlb()
404 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; in r4k_map_address()
1373 tlb = &env->tlb->mmu.r4k.tlb[idx]; in r4k_invalidate_tlb()
[all …]
/qemu/pc-bios/dtb/
H A Dpetalogix-ml605.dts99 xlnx,mmu-dtlb-size = < 0x04 >;
100 xlnx,mmu-itlb-size = < 0x02 >;
101 xlnx,mmu-privileged-instr = < 0x00 >;
102 xlnx,mmu-tlb-access = < 0x03 >;
103 xlnx,mmu-zones = < 0x02 >;
127 xlnx,use-mmu = < 0x03 >;
H A Dpetalogix-s3adsp1800.dts81 xlnx,mmu-dtlb-size = <0x04>;
82 xlnx,mmu-itlb-size = <0x02>;
83 xlnx,mmu-tlb-access = <0x03>;
84 xlnx,mmu-zones = <0x10>;
105 xlnx,use-mmu = <0x03>;
/qemu/target/openrisc/
H A Dmeson.build21 'mmu.c',
/qemu/target/sparc/
H A Dldst_helper.c81 const SparcV9MMU *mmu, const int idx) in ultrasparc_tsb_pointer() argument
87 int ctx = mmu->tag_access & 0x1fffULL; in ultrasparc_tsb_pointer()
88 uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0]; in ultrasparc_tsb_pointer()
93 tsb_register = mmu->sun4v_tsb_pointers[tsb_index]; in ultrasparc_tsb_pointer()
96 tsb_register = mmu->tsb; in ultrasparc_tsb_pointer()
105 uint64_t va = mmu->tag_access >> (3 * page_size + 9); in ultrasparc_tsb_pointer()
/qemu/target/riscv/
H A Dmonitor.c220 if (!riscv_cpu_cfg(env)->mmu) { in hmp_info_mem()
H A Dcpu_cfg_fields.h.inc149 BOOL_FIELD(mmu)
H A Dcpu.c1515 if (cpu->cfg.mmu != value && riscv_cpu_is_vendor(obj)) { in prop_mmu_set()
1521 cpu->cfg.mmu = value; in prop_mmu_set()
1527 bool value = RISCV_CPU(obj)->cfg.mmu; in prop_mmu_get()
2892 .cfg.mmu = true,
2950 .cfg.mmu = true,
3031 .cfg.mmu = true,
3059 .cfg.mmu = true,
3118 .cfg.mmu = true,
3164 .cfg.mmu = true,
/qemu/docs/system/i386/
H A Dkvm-pv.rst41 ``kvm-mmu``
/qemu/target/mips/
H A Dinternal.h156 } mmu; member
/qemu/target/ppc/translate/
H A Dstorage-ctrl-impl.c.inc24 #include "mmu-book3s-v3.h"

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