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Searched refs:lsb (Results 1 – 20 of 20) sorted by relevance

/qemu/target/riscv/
H A Dxthead.decode29 &th_bfext msb lsb rs1 rd
39 @th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd
/qemu/tcg/s390x/
H A Dtcg-target.c.inc543 uint64_t lsb;
554 lsb = c & -c;
558 c &= -lsb;
560 lsb = c & -c;
562 return c == -lsb;
1138 int msb, int lsb, int ofs, int z)
1142 tcg_out16(s, (msb << 8) | (z << 7) | lsb);
1193 int msb, lsb;
1195 /* Achieve wraparound by swapping msb and lsb. */
1197 lsb = clz64(~val) - 1;
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/qemu/target/arm/tcg/
H A Da32.decode46 &bfx rd rn lsb widthm1
47 &bfi rd rn lsb msb
418 @bfx ---- .... ... widthm1:5 rd:4 lsb:5 ... rn:4 &bfx
424 BFCI ---- 0111 110 msb:5 rd:4 lsb:5 001 rn:4 &bfi
H A Dt32.decode43 &bfx !extern rd rn lsb widthm1
44 &bfi !extern rd rn lsb msb
251 &bfx lsb=%imm5_12_6
253 &bfi lsb=%imm5_12_6
H A Dtranslate.c5661 int shift = a->lsb; in op_bfx()
5694 int msb = a->msb, lsb = a->lsb; in trans_BFCI() local
5701 if (msb < lsb) { in trans_BFCI()
5707 width = msb + 1 - lsb; in trans_BFCI()
5716 tcg_gen_deposit_i32(t_rd, t_rd, t_in, lsb, width); in trans_BFCI()
/qemu/target/hexagon/
H A Dgenptr.c714 TCGv lsb = tcg_temp_new(); in gen_cond_call() local
716 tcg_gen_andi_tl(lsb, pred, 1); in gen_cond_call()
717 gen_write_new_pc_pcrel(ctx, pc_off, cond, lsb); in gen_cond_call()
718 tcg_gen_brcondi_tl(cond, lsb, 0, skip); in gen_cond_call()
726 TCGv lsb = tcg_temp_new(); in gen_cond_callr() local
728 tcg_gen_andi_tl(lsb, pred, 1); in gen_cond_callr()
729 tcg_gen_brcondi_tl(cond, lsb, 0, skip); in gen_cond_callr()
H A Dgen_tcg_hvx.h169 TCGv lsb = tcg_temp_new(); \
171 tcg_gen_andi_tl(lsb, PsV, 1); \
172 tcg_gen_brcondi_tl(TCG_COND_NE, lsb, PRED, false_label); \
H A Dmacros.h331 TCGv lsb = tcg_temp_new(); in gen_read_ireg() local
333 tcg_gen_extract_tl(lsb, val, 17, 7); in gen_read_ireg()
335 tcg_gen_deposit_tl(result, msb, lsb, 0, 7); in gen_read_ireg()
/qemu/target/mips/tcg/system/
H A Dtlb_helper.c643 uint64_t lsb = 0; in walk_directory() local
662 lsb = BIT_ULL(w) >> 6; in walk_directory()
663 *pw_entrylo0 = entry & ~lsb; /* even page */ in walk_directory()
664 *pw_entrylo1 = entry | lsb; /* odd page */ in walk_directory()
/qemu/target/riscv/insn_trans/
H A Dtrans_rvb.c.inc322 /* Extract the msb to the lsb in each byte */
326 /* Replicate the lsb of each byte across the byte. */
H A Dtrans_xthead.c.inc164 if (a->lsb <= a->msb) {
165 f(dest, source, a->lsb, a->msb - a->lsb + 1);
/qemu/tcg/sparc64/
H A Dtcg-target.c.inc432 tcg_target_long test, lsb;
462 lsb = ctz64(arg);
463 test = (tcg_target_long)arg >> lsb;
464 if (lsb > 10 && test == extract64(test, 0, 21)) {
466 tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX);
470 tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX);
/qemu/tcg/mips/
H A Dtcg-target.c.inc404 TCGReg rs, int msb, int lsb)
412 inst |= (lsb & 0x1F) << 6;
418 int msb, int lsb)
420 if (lsb >= 32) {
423 lsb -= 32;
428 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
/qemu/disas/
H A Dmips.c4247 unsigned int lsb, msb, msbd; in print_insn_args() local
4249 lsb = 0; in print_insn_args()
4275 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT; in print_insn_args()
4276 (*info->fprintf_func) (info->stream, "0x%x", lsb); in print_insn_args()
4281 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); in print_insn_args()
4416 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32; in print_insn_args()
4417 (*info->fprintf_func) (info->stream, "0x%x", lsb); in print_insn_args()
4422 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); in print_insn_args()
/qemu/tcg/ppc/
H A Dtcg-target.c.inc1286 uint32_t lsb, test;
1297 lsb = test & -test;
1298 test += lsb;
1303 *me = clz32(lsb);
1310 uint64_t lsb;
1316 lsb = c & -c;
1318 if (c == -lsb) {
1320 *me = clz64(lsb);
1324 if (lsb == 1 && (c & (c + 1)) == 0) {
/qemu/target/mips/tcg/
H A Dtranslate.c4621 int rs, int lsb, int msb) in gen_bitops() argument
4629 if (lsb + msb > 31) { in gen_bitops()
4633 tcg_gen_extract_tl(t0, t1, lsb, msb + 1); in gen_bitops()
4644 lsb += 32; in gen_bitops()
4651 if (lsb + msb > 63) { in gen_bitops()
4654 tcg_gen_extract_tl(t0, t1, lsb, msb + 1); in gen_bitops()
4658 if (lsb > msb) { in gen_bitops()
4662 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); in gen_bitops()
4667 lsb += 32; in gen_bitops()
4673 if (lsb > msb) { in gen_bitops()
[all …]
H A Ddsp_helper.c2923 uint32_t pos, size, msb, lsb; \
2934 lsb = pos; \
2936 if (lsb > msb || (msb > TARGET_LONG_BITS)) { \
/qemu/fpu/
H A Dsoftfloat-parts.c.inc1132 * Rounding is not in the low word -- shift lsb to bit 2,
/qemu/target/ppc/
H A Dint_helper.c2058 VUPK(lsb, s16, s8, UPKLO)
/qemu/tests/functional/acpi-bits/bits-tests/
H A Dsmbios.py22039 # if lsb is 1, address is in IO space. otherwise, memory-mapped