Searched refs:intr_mask (Results 1 – 5 of 5) sorted by relevance
75 level = !!(s->intr & s->intr_mask); in xilinx_pcie_update_intr()199 val = s->intr_mask; in xilinx_pcie_root_config_read()244 s->intr_mask = val; in xilinx_pcie_root_config_write()
59 uint32_t intr_mask; member
62 uint32_t state = s->intr_status & ~(s->intr_mask | MPI_HIS_IOP_DOORBELL_STATUS); in mptsas_update_interrupt()806 save_mask = s->intr_mask; in mptsas_soft_reset()807 s->intr_mask = MPI_HIM_DIM | MPI_HIM_RIM; in mptsas_soft_reset()812 s->intr_mask = save_mask; in mptsas_soft_reset()952 s->intr_mask = MPI_HIM_DIM | MPI_HIM_RIM; in mptsas_hard_reset()1020 ret = s->intr_mask; in mptsas_mmio_read()1061 s->intr_mask = val & (MPI_HIM_RIM | MPI_HIM_DIM); in mptsas_mmio_write()1387 VMSTATE_UINT32(intr_mask, MPTSASState),
58 uint32_t intr_mask; member
93 uint32_t intr_mask; member147 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) != in DECLARE_OBJ_CHECKERS()2050 retval = s->intr_mask; in megasas_mmio_read()2106 s->intr_mask = val; in megasas_mmio_write()2273 s->intr_mask = MEGASAS_INTR_DISABLED_MASK; in megasas_soft_reset()2296 VMSTATE_UINT32(intr_mask, MegasasState),2314 VMSTATE_UINT32(intr_mask, MegasasState),