| /qemu/hw/misc/ |
| H A D | mips_cmgcr.c | 32 static inline void update_gcr_base(MIPSGCRState *gcr, uint64_t val) in update_gcr_base() argument
37 gcr->gcr_base = val & GCR_BASE_GCRBASE_MSK; in update_gcr_base()
38 memory_region_set_address(&gcr->iomem, gcr->gcr_base); in update_gcr_base()
42 mips_cpu->env.CP0_CMGCRBase = gcr->gcr_base >> 4; in update_gcr_base()
46 static inline void update_cpc_base(MIPSGCRState *gcr, uint64_t val) in update_cpc_base() argument
48 if (is_cpc_connected(gcr)) { in update_cpc_base()
49 gcr->cpc_base = val & GCR_CPC_BASE_MSK; in update_cpc_base()
51 memory_region_set_address(gcr->cpc_mr, in update_cpc_base()
52 gcr->cpc_base & GCR_CPC_BASE_CPCBASE_MSK); in update_cpc_base()
53 memory_region_set_enabled(gcr->cpc_mr, in update_cpc_base()
[all …]
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| /qemu/hw/mips/ |
| H A D | cps.c | 150 object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); in mips_cps_realize()
151 object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, in mips_cps_realize()
153 object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800, in mips_cps_realize()
155 object_property_set_int(OBJECT(&s->gcr), "gcr-base", gcr_base, in mips_cps_realize()
157 object_property_set_link(OBJECT(&s->gcr), "gic", OBJECT(&s->gic.mr), in mips_cps_realize()
159 object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr), in mips_cps_realize()
161 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { in mips_cps_realize()
166 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0)); in mips_cps_realize()
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| /qemu/hw/arm/ |
| H A D | npcm7xx.c | 423 object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR); in npcm7xx_init()
424 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), in npcm7xx_init()
527 object_property_set_int(OBJECT(&s->gcr), "disabled-modules", in npcm7xx_realize()
529 object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram)); in npcm7xx_realize()
530 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { in npcm7xx_realize()
533 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA); in npcm7xx_realize()
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| H A D | npcm8xx.c | 417 object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM8XX_GCR); in npcm8xx_init()
418 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), in npcm8xx_init()
543 object_property_set_int(OBJECT(&s->gcr), "disabled-modules", in npcm8xx_realize()
545 object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram)); in npcm8xx_realize()
546 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { in npcm8xx_realize()
549 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM8XX_GCR_BA); in npcm8xx_realize()
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| H A D | omap1.c | 2432 uint8_t gcr; member
2451 return s->gcr; in omap_pwt_read()
2479 ((s->gcr & 2) ? 1 : 154) / in omap_pwt_write()
2498 s->gcr = value & 3; in omap_pwt_write()
2516 s->gcr = 0; in omap_pwt_reset()
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| /qemu/include/hw/mips/ |
| H A D | cps.h | 44 MIPSGCRState gcr; member
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| /qemu/include/hw/arm/ |
| H A D | npcm8xx.h | 89 NPCMGCRState gcr; member
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| H A D | npcm7xx.h | 92 NPCMGCRState gcr; member
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| /qemu/hw/intc/ |
| H A D | openpic.c | 551 opp->gcr &= ~opp->mpic_mode_mask; in openpic_gcr_write()
552 opp->gcr |= val & opp->mpic_mode_mask; in openpic_gcr_write()
638 retval = opp->gcr; in openpic_gbl_read()
1259 opp->gcr = GCR_RESET; in openpic_reset()
1315 opp->gcr = 0; in openpic_reset()
1472 VMSTATE_UINT32(gcr, OpenPICState),
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| /qemu/include/hw/ppc/ |
| H A D | openpic.h | 155 uint32_t gcr; /* Global configuration register */ member
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| /qemu/hw/dma/ |
| H A D | omap_dma.c | 115 uint32_t gcr; member
689 s->gcr = 0x0004;
1362 s->gcr = value;
1388 *ret = s->gcr;
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