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Searched refs:clk (Results 1 – 25 of 53) sorted by relevance

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/qemu/hw/core/
H A Dclock.c23 void clock_setup_canonical_path(Clock *clk) in clock_setup_canonical_path() argument
25 g_free(clk->canonical_path); in clock_setup_canonical_path()
26 clk->canonical_path = object_get_canonical_path(OBJECT(clk)); in clock_setup_canonical_path()
32 Clock *clk; in clock_new() local
38 clk = CLOCK(obj); in clock_new()
39 clock_setup_canonical_path(clk); in clock_new()
41 return clk; in clock_new()
44 void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque, in clock_set_callback() argument
47 assert(OBJECT(clk)->parent); in clock_set_callback()
48 clk->callback = cb; in clock_set_callback()
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H A Dqdev-clock.c25 bool alias, bool output, Clock *clk) in qdev_init_clocklist() argument
43 ncl->clock = clk; in qdev_init_clocklist()
70 Clock *clk = CLOCK(object_new(TYPE_CLOCK)); in qdev_init_clock_out() local
71 object_property_add_child(OBJECT(dev), name, OBJECT(clk)); in qdev_init_clock_out()
73 qdev_init_clocklist(dev, name, false, true, clk); in qdev_init_clock_out()
74 return clk; in qdev_init_clock_out()
81 Clock *clk = CLOCK(object_new(TYPE_CLOCK)); in qdev_init_clock_in() local
82 object_property_add_child(OBJECT(dev), name, OBJECT(clk)); in qdev_init_clock_in()
84 qdev_init_clocklist(dev, name, false, false, clk); in qdev_init_clock_in()
86 clock_set_callback(clk, callback, opaque, events); in qdev_init_clock_in()
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H A Dclock-vmstate.c19 Clock *clk = opaque; in muldiv_needed() local
21 return clk->multiplier != 1 || clk->divider != 1; in muldiv_needed()
26 Clock *clk = opaque; in clock_pre_load() local
33 clk->multiplier = 1; in clock_pre_load()
34 clk->divider = 1; in clock_pre_load()
H A Dtrace-events26 clock_set_source(const char *clk, const char *src) "'%s', src='%s'"
27 clock_disconnect(const char *clk) "'%s'"
28 clock_set(const char *clk, uint64_t old, uint64_t new) "'%s', %"PRIu64"Hz->%"PRIu64"Hz"
29 clock_propagate(const char *clk) "'%s'"
30 clock_update(const char *clk, const char *src, uint64_t hz, int cb) "'%s', src='%s', val=%"PRIu64"H…
31 clock_set_mul_div(const char *clk, uint32_t oldmul, uint32_t mul, uint32_t olddiv, uint32_t div) "'…
/qemu/hw/misc/
H A Domap_clk.c27 struct clk { struct
30 struct clk *parent; argument
31 struct clk *child1; argument
32 struct clk *sibling; argument
50 static struct clk xtal_osc12m = { argument
56 static struct clk xtal_osc32k = {
62 static struct clk ck_ref = {
71 static struct clk dpll1 = {
78 static struct clk dpll2 = {
84 static struct clk dpll3 = {
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H A Dnpcm_clk.c214 uint32_t con = s->clk->regs[s->reg]; in npcm7xx_clk_update_pll()
232 uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset, in npcm7xx_clk_update_sel()
261 (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1); in divide_by_reg_divisor()
272 extract32(s->clk->regs[s->reg], s->offset, s->len); in shift_by_reg_divisor()
291 static void npcm7xx_clk_update_all_plls(NPCMCLKState *clk) in npcm7xx_clk_update_all_plls() argument
296 npcm7xx_clk_update_pll(&clk->plls[i]); in npcm7xx_clk_update_all_plls()
300 static void npcm7xx_clk_update_all_sels(NPCMCLKState *clk) in npcm7xx_clk_update_all_sels() argument
305 npcm7xx_clk_update_sel(&clk->sels[i]); in npcm7xx_clk_update_all_sels()
309 static void npcm7xx_clk_update_all_dividers(NPCMCLKState *clk) in npcm7xx_clk_update_all_dividers() argument
314 npcm7xx_clk_update_divider(&clk->dividers[i]); in npcm7xx_clk_update_all_dividers()
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H A Dstm32l4x5_syscfg.c231 s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0); in stm32l4x5_syscfg_init()
237 if (!clock_has_source(s->clk)) { in stm32l4x5_syscfg_realize()
257 VMSTATE_CLOCK(clk, Stm32l4x5SyscfgState),
/qemu/include/hw/
H A Dclock.h114 void clock_setup_canonical_path(Clock *clk);
141 void clock_set_callback(Clock *clk, ClockCallback *cb,
154 void clock_set_source(Clock *clk, Clock *src);
166 static inline bool clock_has_source(const Clock *clk) in clock_has_source() argument
168 return clk->source != NULL; in clock_has_source()
180 bool clock_set(Clock *clk, uint64_t value);
182 static inline bool clock_set_hz(Clock *clk, unsigned hz) in clock_set_hz() argument
184 return clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz)); in clock_set_hz()
187 static inline bool clock_set_ns(Clock *clk, unsigned ns) in clock_set_ns() argument
189 return clock_set(clk, CLOCK_PERIOD_FROM_NS(ns)); in clock_set_ns()
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/qemu/hw/acpi/
H A Dvmclock.c69 if (!vms->clk) { in vmclock_update_guest()
73 seq_count = le32_to_cpu(vms->clk->seq_count) | 1; in vmclock_update_guest()
74 vms->clk->seq_count = cpu_to_le32(seq_count); in vmclock_update_guest()
78 disruption_marker = le64_to_cpu(vms->clk->disruption_marker); in vmclock_update_guest()
80 vms->clk->disruption_marker = cpu_to_le64(disruption_marker); in vmclock_update_guest()
84 vms->clk->seq_count = cpu_to_le32(seq_count + 1); in vmclock_update_guest()
141 vms->clk = memory_region_get_ram_ptr(&vms->clk_page); in vmclock_realize()
142 memset(vms->clk, 0, VMCLOCK_SIZE); in vmclock_realize()
144 vms->clk->magic = cpu_to_le32(VMCLOCK_MAGIC); in vmclock_realize()
145 vms->clk->size = cpu_to_le16(VMCLOCK_SIZE); in vmclock_realize()
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/qemu/include/hw/arm/
H A Domap.h49 typedef struct clk *omap_clk;
52 void omap_clk_adduser(struct clk *clk, qemu_irq user);
53 void omap_clk_get(omap_clk clk);
54 void omap_clk_put(omap_clk clk);
55 void omap_clk_onoff(omap_clk clk, int on);
56 void omap_clk_canidle(omap_clk clk, int can);
57 void omap_clk_setrate(omap_clk clk, int divide, int multiply);
58 int64_t omap_clk_getrate(omap_clk clk);
59 void omap_clk_reparent(omap_clk clk, omap_clk parent);
81 void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk);
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/qemu/hw/arm/
H A Domap1.c110 omap_clk clk; member
194 timer->rate = on ? omap_clk_getrate(timer->clk) : 0; in omap_timer_clk_update()
200 omap_clk_adduser(timer->clk, in omap_timer_clk_setup()
202 timer->rate = omap_clk_getrate(timer->clk); in omap_timer_clk_setup()
282 qemu_irq irq, omap_clk clk) in omap_mpu_timer_init() argument
287 s->clk = clk; in omap_mpu_timer_init()
362 omap_clk_get(s->timer.clk); in omap_wd_timer_write()
368 omap_clk_put(s->timer.clk); in omap_wd_timer_write()
395 omap_clk_get(s->timer.clk); in omap_wd_timer_reset()
411 qemu_irq irq, omap_clk clk) in omap_wd_timer_init() argument
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H A Dnpcm7xx.c426 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK); in npcm7xx_init()
536 sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort); in npcm7xx_realize()
537 sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA); in npcm7xx_realize()
552 DEVICE(&s->clk), "adc-clock")); in npcm7xx_realize()
568 DEVICE(&s->clk), "timer-clock")); in npcm7xx_realize()
585 qdev_get_gpio_in_named(DEVICE(&s->clk), in npcm7xx_realize()
652 DEVICE(&s->clk), "apb3-clock")); in npcm7xx_realize()
664 qdev_get_clock_out(DEVICE(&s->clk), in npcm7xx_realize()
H A Dnpcm8xx.c420 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM8XX_CLK); in npcm8xx_init()
552 sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort); in npcm8xx_realize()
553 sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM8XX_CLK_BA); in npcm8xx_realize()
566 DEVICE(&s->clk), "adc-clock")); in npcm8xx_realize()
582 DEVICE(&s->clk), "timer-clock")); in npcm8xx_realize()
599 qdev_get_gpio_in_named(DEVICE(&s->clk), in npcm8xx_realize()
673 DEVICE(&s->clk), "apb3-clock")); in npcm8xx_realize()
685 qdev_get_clock_out(DEVICE(&s->clk), in npcm8xx_realize()
/qemu/rust/qemu-api/src/
H A Dqdev.rs285 let clk = bindings::qdev_init_clock_in( in init_clock_in() localVariable
293 let clk: &Clock = Clock::from_raw(clk); in init_clock_in() localVariable
294 Owned::from(clk) in init_clock_in()
326 let clk = bindings::qdev_init_clock_out(self.upcast().as_mut_ptr(), cstr.as_ptr()); in init_clock_out() localVariable
328 let clk: &Clock = Clock::from_raw(clk); in init_clock_out() localVariable
329 Owned::from(clk) in init_clock_out()
/qemu/hw/gpio/
H A Domap_gpio.c49 void *clk; member
218 if (!s->clk) { in omap_gpio_realize()
223 void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk) in omap_gpio_set_clk() argument
225 gpio->clk = clk; in omap_gpio_set_clk()
H A Dstm32l4x5_gpio.c253 uint32_t clock_freq_hz = clock_get_hz(s->clk); in clock_freq_get()
410 s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0); in stm32l4x5_gpio_init()
422 if (!clock_has_source(s->clk)) { in stm32l4x5_gpio_realize()
445 VMSTATE_CLOCK(clk, Stm32l4x5GpioState),
/qemu/include/hw/ppc/
H A Dppc.h18 static inline void clk_setup (clk_setup_t *clk, uint32_t freq) in clk_setup() argument
20 if (clk->cb != NULL) in clk_setup()
21 (*clk->cb)(clk->opaque, freq); in clk_setup()
/qemu/include/hw/misc/
H A Dnpcm_clk.h99 NPCMCLKState *clk; member
120 NPCMCLKState *clk; member
145 NPCMCLKState *clk; member
/qemu/hw/ssi/
H A Dbcm2835_spi.c121 readval = s->clk & 0xffff; in bcm2835_spi_read()
200 s->clk = value & 0xffff; in bcm2835_spi_write()
245 s->clk = 0; in bcm2835_spi_reset()
259 VMSTATE_UINT32(clk, BCM2835SPIState),
/qemu/hw/timer/
H A Dsse-counter.c127 return s->ns_then + clock_ticks_to_ns(s->clk, tick); in sse_counter_tick_to_time()
150 ticks = clock_ns_to_ticks(s->clk, now - s->ns_then); in sse_counter_for_timestamp()
421 s->clk = qdev_init_clock_in(DEVICE(obj), "CLK", sse_clk_callback, s, in sse_counter_init()
435 if (!clock_has_source(s->clk)) { in sse_counter_realize()
446 VMSTATE_CLOCK(clk, SSECounter),
H A Dstellaris-gptm.c43 tick += clock_ticks_to_ns(s->clk, count); in gptm_reload()
267 VMSTATE_CLOCK(clk, gptm_state),
295 s->clk = qdev_init_clock_in(dev, "clk", NULL, NULL, 0); in stellaris_gptm_init()
302 if (!clock_has_source(s->clk)) { in stellaris_gptm_realize()
/qemu/hw/char/
H A Dpl011.c348 uint64_t clk; in pl011_get_baudrate() local
354 clk = clock_get_hz(s->clk); in pl011_get_baudrate()
355 return (clk / ((s->ibrd << 6) + s->fbrd)) << 2; in pl011_get_baudrate()
361 clock_get_hz(s->clk), in pl011_trace_baudrate_change()
559 VMSTATE_CLOCK(clk, PL011State),
638 s->clk = qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, s, in pl011_init()
/qemu/hw/intc/
H A Domap_intc.c368 void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk) in omap_intc_set_iclk() argument
370 intc->iclk = clk; in omap_intc_set_iclk()
373 void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk) in omap_intc_set_fclk() argument
375 intc->fclk = clk; in omap_intc_set_fclk()
/qemu/hw/input/
H A Dpl050.c35 VMSTATE_UINT32(clk, PL050State),
108 return s->clk; in pl050_read()
139 s->clk = value; in pl050_write()
/qemu/hw/i2c/
H A Domap_i2c.c504 void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk) in omap_i2c_set_iclk() argument
506 i2c->iclk = clk; in omap_i2c_set_iclk()
509 void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk) in omap_i2c_set_fclk() argument
511 i2c->fclk = clk; in omap_i2c_set_fclk()

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