214     uint32_t con = s->clk->regs[s->reg];  in npcm7xx_clk_update_pll()
232     uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset,  in npcm7xx_clk_update_sel()
261             (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1);  in divide_by_reg_divisor()
272         extract32(s->clk->regs[s->reg], s->offset, s->len);  in shift_by_reg_divisor()
291 static void npcm7xx_clk_update_all_plls(NPCMCLKState *clk)  in npcm7xx_clk_update_all_plls()  argument
296         npcm7xx_clk_update_pll(&clk->plls[i]);  in npcm7xx_clk_update_all_plls()
300 static void npcm7xx_clk_update_all_sels(NPCMCLKState *clk)  in npcm7xx_clk_update_all_sels()  argument
305         npcm7xx_clk_update_sel(&clk->sels[i]);  in npcm7xx_clk_update_all_sels()
309 static void npcm7xx_clk_update_all_dividers(NPCMCLKState *clk)  in npcm7xx_clk_update_all_dividers()  argument
314         npcm7xx_clk_update_divider(&clk->dividers[i]);  in npcm7xx_clk_update_all_dividers()
318 static void npcm7xx_clk_update_all_clocks(NPCMCLKState *clk)  in npcm7xx_clk_update_all_clocks()  argument
320     clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);  in npcm7xx_clk_update_all_clocks()
321     npcm7xx_clk_update_all_plls(clk);  in npcm7xx_clk_update_all_clocks()
322     npcm7xx_clk_update_all_sels(clk);  in npcm7xx_clk_update_all_clocks()
323     npcm7xx_clk_update_all_dividers(clk);  in npcm7xx_clk_update_all_clocks()
728         NPCMCLKState *clk, const PLLInitInfo *init_info)  in npcm7xx_init_clock_pll()  argument
731     pll->clk = clk;  in npcm7xx_init_clock_pll()
734         qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk),  in npcm7xx_init_clock_pll()
740         NPCMCLKState *clk, const SELInitInfo *init_info)  in npcm7xx_init_clock_sel()  argument
745     sel->clk = clk;  in npcm7xx_init_clock_sel()
751         qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk),  in npcm7xx_init_clock_sel()
757         NPCMCLKState *clk, const DividerInitInfo *init_info)  in npcm7xx_init_clock_divider()  argument
760     div->clk = clk;  in npcm7xx_init_clock_divider()
771         qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk),  in npcm7xx_init_clock_divider()
776 static Clock *npcm7xx_get_clock(NPCMCLKState *clk, ClockSrcType type,  in npcm7xx_get_clock()  argument
781         return clk->clkref;  in npcm7xx_get_clock()
783         return clk->plls[index].clock_out;  in npcm7xx_get_clock()
785         return clk->sels[index].clock_out;  in npcm7xx_get_clock()
787         return clk->dividers[index].clock_out;  in npcm7xx_get_clock()
793 static void npcm7xx_connect_clocks(NPCMCLKState *clk)  in npcm7xx_connect_clocks()  argument
799         src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type,  in npcm7xx_connect_clocks()
801         clock_set_source(clk->plls[i].clock_in, src);  in npcm7xx_connect_clocks()
805             src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j],  in npcm7xx_connect_clocks()
807             clock_set_source(clk->sels[i].clock_in[j], src);  in npcm7xx_connect_clocks()
811         src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type,  in npcm7xx_connect_clocks()
813         clock_set_source(clk->dividers[i].clock_in, src);  in npcm7xx_connect_clocks()
937     NPCMCLKState *clk = NPCM_CLK(opaque);  in npcm7xx_clk_perform_watchdog_reset()  local
941     rcr = clk->regs[NPCM7XX_CLK_WD0RCR + n];  in npcm7xx_clk_perform_watchdog_reset()
1026         NPCMCLKState *clk = opaque;  in npcm_clk_post_load()  local
1028         npcm7xx_clk_update_all_clocks(clk);  in npcm_clk_post_load()