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Searched refs:bcr (Results 1 – 13 of 13) sorted by relevance

/qemu/hw/ppc/
H A Dppc4xx_sdram.c128 static void sdram_bank_set_bcr(Ppc4xxSdramBank *bank, uint32_t bcr, in sdram_bank_set_bcr() argument
134 bank->bcr = bcr; in sdram_bank_set_bcr()
137 if (enabled && (bcr & 1)) { in sdram_bank_set_bcr()
153 uint32_t bcr; in sdram_ddr_bcr() local
157 bcr = 0; in sdram_ddr_bcr()
160 bcr = 0x20000; in sdram_ddr_bcr()
163 bcr = 0x40000; in sdram_ddr_bcr()
166 bcr = 0x60000; in sdram_ddr_bcr()
169 bcr = 0x80000; in sdram_ddr_bcr()
172 bcr = 0xA0000; in sdram_ddr_bcr()
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H A Dppc4xx_devs.c358 ret = ebc->bcr[0]; in dcr_read_ebc()
361 ret = ebc->bcr[1]; in dcr_read_ebc()
364 ret = ebc->bcr[2]; in dcr_read_ebc()
367 ret = ebc->bcr[3]; in dcr_read_ebc()
370 ret = ebc->bcr[4]; in dcr_read_ebc()
373 ret = ebc->bcr[5]; in dcr_read_ebc()
376 ret = ebc->bcr[6]; in dcr_read_ebc()
379 ret = ebc->bcr[7]; in dcr_read_ebc()
496 ebc->bcr[0] = 0xFFE28000; in ppc405_ebc_reset()
499 ebc->bcr[i] = 0x00000000; in ppc405_ebc_reset()
H A Dtrace-events178 …ram_init(uint64_t base, uint64_t size, uint32_t bcr) "Init RAM area 0x%" PRIx64 " size 0x%" PRIx64…
/qemu/hw/net/
H A Dpcnet.h27 #define BCR_TMAULOOP(S) !!((S)->bcr[BCR_MC ] & 0x4000)
28 #define BCR_APROMWE(S) !!((S)->bcr[BCR_MC ] & 0x0100)
29 #define BCR_DWIO(S) !!((S)->bcr[BCR_BSBC] & 0x0080)
30 #define BCR_SSIZE32(S) !!((S)->bcr[BCR_SWS ] & 0x0100)
31 #define BCR_SWSTYLE(S) ((S)->bcr[BCR_SWS ] & 0x00FF)
43 uint16_t bcr[32]; member
H A Dpcnet.c682 s->bcr[BCR_BSBC] &= ~0x0080; in pcnet_s_reset()
1515 s->bcr[rap] = val; in pcnet_bcr_writew()
1531 val = s->bcr[rap] & ~0x8000; in pcnet_bcr_readw()
1535 val = rap < 32 ? s->bcr[rap] : 0; in pcnet_bcr_readw()
1548 s->bcr[BCR_MSRDA] = 0x0005; in pcnet_h_reset()
1549 s->bcr[BCR_MSWRA] = 0x0005; in pcnet_h_reset()
1550 s->bcr[BCR_MC ] = 0x0002; in pcnet_h_reset()
1551 s->bcr[BCR_LNKST] = 0x00c0; in pcnet_h_reset()
1552 s->bcr[BCR_LED1 ] = 0x0084; in pcnet_h_reset()
1553 s->bcr[BCR_LED2 ] = 0x0088; in pcnet_h_reset()
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/qemu/target/arm/
H A Dhyp_gdbstub.c60 .bcr = 0x1, /* BCR E=1, enable */ in insert_hw_breakpoint()
68 brk.bcr = deposit32(brk.bcr, 1, 2, 0x3); /* PMC = 11 */ in insert_hw_breakpoint()
69 brk.bcr = deposit32(brk.bcr, 5, 4, 0xf); /* BAS = RES1 */ in insert_hw_breakpoint()
H A Ddebug_helper.c178 uint64_t bcr = env->cp15.dbgbcr[lbn]; in linked_bp_matches() local
196 bcr = env->cp15.dbgbcr[lbn]; in linked_bp_matches()
198 if (extract64(bcr, 0, 1) == 0) { in linked_bp_matches()
203 bt = extract64(bcr, 20, 4); in linked_bp_matches()
659 uint64_t bcr = env->cp15.dbgbcr[n]; in hw_breakpoint_update() local
669 if (!extract64(bcr, 0, 1)) { in hw_breakpoint_update()
674 bt = extract64(bcr, 20, 4); in hw_breakpoint_update()
709 int bas = extract64(bcr, 5, 4); in hw_breakpoint_update()
H A Dinternals.h1926 uint64_t bcr; member
H A Dkvm.c1468 ptr->dbg_bcr[i] = bp->bcr; in kvm_arm_copy_hw_debug_data()
/qemu/include/hw/ppc/
H A Dppc4xx.h91 uint32_t bcr[8]; member
105 uint32_t bcr; member
/qemu/hw/sh4/
H A Dr2d.c73 uint16_t bcr; member
/qemu/target/arm/hvf/
H A Dhvf.c2219 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], bp->bcr); in hvf_put_gdbstub_debug_registers()
/qemu/tcg/s390x/
H A Dtcg-target.c.inc3060 /* fast-bcr-serialization facility (45) is present */