Searched refs:SD_CTL_STREAM_RESET (Results 1 – 2 of 2) sorted by relevance
131 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ macro
584 st->ctl = SD_STS_FIFO_READY << 24 | SD_CTL_STREAM_RESET; in intel_hda_set_st_ctl()