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Searched refs:RVU (Results 1 – 5 of 5) sorted by relevance

/qemu/target/riscv/
H A Dcpu.c44 RVC, RVS, RVU, RVH, RVG, RVB, 0};
1165 MISA_EXT_INFO(RVU, "u", "User-level instructions"),
2010 .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU,
2935 .misa_ext = RVI | RVM | RVA | RVC | RVU,
2944 .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU,
2963 .misa_ext = RVI | RVM | RVC | RVU,
3026 .misa_ext = RVG | RVC | RVS | RVU,
3054 .misa_ext = RVG | RVC | RVS | RVU | RVH | RVV,
3114 .misa_ext = RVG | RVC | RVS | RVU | RVH,
3149 .misa_ext = RVG | RVC | RVB | RVS | RVU,
H A Dcsr.c477 if (riscv_has_ext(env, RVU)) { in umode()
1071 inh_avail_mask |= riscv_has_ext(env, RVU) ? MCYCLECFG_BIT_UINH : 0; in write_mcyclecfg()
1074 riscv_has_ext(env, RVU)) ? MCYCLECFG_BIT_VUINH : 0; in write_mcyclecfg()
1097 inh_avail_mask |= riscv_has_ext(env, RVU) ? MCYCLECFGH_BIT_UINH : 0; in write_mcyclecfgh()
1100 riscv_has_ext(env, RVU)) ? MCYCLECFGH_BIT_VUINH : 0; in write_mcyclecfgh()
1124 inh_avail_mask |= riscv_has_ext(env, RVU) ? MINSTRETCFG_BIT_UINH : 0; in write_minstretcfg()
1127 riscv_has_ext(env, RVU)) ? MINSTRETCFG_BIT_VUINH : 0; in write_minstretcfg()
1148 inh_avail_mask |= riscv_has_ext(env, RVU) ? MINSTRETCFGH_BIT_UINH : 0; in write_minstretcfgh()
1151 riscv_has_ext(env, RVU)) ? MINSTRETCFGH_BIT_VUINH : 0; in write_minstretcfgh()
1182 inh_avail_mask |= riscv_has_ext(env, RVU) ? MHPMEVENT_BIT_UINH : 0; in write_mhpmevent()
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H A Dop_helper.c406 riscv_has_ext(env, RVU) ? PRV_U : PRV_M); in helper_mret()
H A Dcpu.h68 #define RVU RV('U') macro
/qemu/target/riscv/tcg/
H A Dtcg-cpu.c602 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { in riscv_cpu_validate_set_extensions()
1288 MISA_CFG(RVU, true),