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Searched refs:RISCV_IOMMU_REG_CQCSR (Results 1 – 4 of 4) sorted by relevance

/qemu/tests/qtest/
H A Driscv-iommu-test.c64 reg = riscv_iommu_read_reg32(r_iommu, RISCV_IOMMU_REG_CQCSR); in test_reg_reset()
153 reg = riscv_iommu_read_reg32(r_iommu, RISCV_IOMMU_REG_CQCSR); in test_iommu_init_queues()
155 riscv_iommu_write_reg32(r_iommu, RISCV_IOMMU_REG_CQCSR, reg); in test_iommu_init_queues()
157 qtest_wait_for_queue_active(r_iommu, RISCV_IOMMU_REG_CQCSR); in test_iommu_init_queues()
/qemu/tests/qtest/libqos/
H A Driscv-iommu.h45 #define RISCV_IOMMU_REG_CQCSR 0x0048 macro
/qemu/hw/riscv/
H A Driscv-iommu.c1643 ctrl = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_CQCSR); in riscv_iommu_process_cq_tail()
1659 riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_CQCSR, in riscv_iommu_process_cq_tail()
1677 riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_CQCSR, in riscv_iommu_process_cq_tail()
1800 riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_CQCSR, in riscv_iommu_process_cq_tail()
1820 uint32_t ctrl_set = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_CQCSR); in riscv_iommu_process_cq_control()
1845 riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_CQCSR, ctrl_set, ctrl_clr); in riscv_iommu_process_cq_control()
1982 cqcsr = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_CQCSR); in riscv_iommu_update_ipsr()
2101 case RISCV_IOMMU_REG_CQCSR: in riscv_iommu_mmio_write()
2395 stl_le_p(&s->regs_wc[RISCV_IOMMU_REG_CQCSR], RISCV_IOMMU_CQCSR_CQMF | in riscv_iommu_realize()
2397 stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_CQCSR], RISCV_IOMMU_CQCSR_CQON | in riscv_iommu_realize()
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H A Driscv-iommu-bits.h159 #define RISCV_IOMMU_REG_CQCSR 0x0048 macro