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Searched refs:PPC_BIT32 (Results 1 – 7 of 7) sorted by relevance

/qemu/include/hw/ppc/
H A Dxive2_regs.h21 #define TM2_W2_VALID PPC_BIT32(0)
22 #define TM2_W2_HW PPC_BIT32(1)
33 #define TM2_QW3W2_LP PPC_BIT32(6)
34 #define TM2_QW3W2_LE PPC_BIT32(7)
60 #define END2_W0_VALID PPC_BIT32(0) /* "v" bit */
61 #define END2_W0_ENQUEUE PPC_BIT32(5) /* "q" bit */
62 #define END2_W0_UCOND_NOTIFY PPC_BIT32(6) /* "n" bit */
63 #define END2_W0_SILENT_ESCALATE PPC_BIT32(7) /* "s" bit */
64 #define END2_W0_BACKLOG PPC_BIT32(8) /* "b" bit */
65 #define END2_W0_PRECL_ESC_CTL PPC_BIT32(9) /* "p" bit */
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H A Dxive_regs.h93 #define TM_QW0W2_VU PPC_BIT32(0)
95 #define TM_QW1W2_VO PPC_BIT32(0)
97 #define TM_QW2W2_VP PPC_BIT32(0)
99 #define TM_QW3W2_VT PPC_BIT32(0)
100 #define TM_QW3W2_LP PPC_BIT32(6)
101 #define TM_QW3W2_LE PPC_BIT32(7)
102 #define TM_QW3W2_T PPC_BIT32(31)
227 #define END_W0_VALID PPC_BIT32(0) /* "v" bit */
228 #define END_W0_ENQUEUE PPC_BIT32(1) /* "q" bit */
229 #define END_W0_UCOND_NOTIFY PPC_BIT32(2) /* "n" bit */
[all …]
/qemu/tests/qtest/
H A Dpnv-xive2-common.h13 #define PPC_BIT32(bit) (0x80000000 >> (bit)) macro
16 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
17 PPC_BIT32(bs))
H A Dpnv-host-i2c-test.c16 #define PPC_BIT32(bit) (0x80000000 >> (bit)) macro
19 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
20 PPC_BIT32(bs))
/qemu/target/ppc/
H A Dcpu.h46 #define PPC_BIT32(bit) (0x80000000 >> (bit)) macro
49 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
50 PPC_BIT32(bs))
/qemu/hw/ppc/
H A Dpnv_core.c646 if (offset & PPC_BIT32(16 + i)) { in pnv_qme_power10_xscom_write()
/qemu/target/ppc/translate/
H A Dvsx-impl.c.inc1456 if (ctx->opcode & PPC_BIT32(25)) { \