/qemu/tests/tcg/hexagon/ |
H A D | usr.c | 423 #define TEST_x_OP_x(RESTYPE, CHECKFN, SRCTYPE, FUNC, SRC, RES, USR_RES) \ argument 428 result = FUNC(src, &usr_result); \ 433 #define TEST_R_OP_R(FUNC, SRC, RES, USR_RES) \ argument 434 TEST_x_OP_x(uint32_t, check32, uint32_t, FUNC, SRC, RES, USR_RES) 436 #define TEST_R_OP_P(FUNC, SRC, RES, USR_RES) \ argument 437 TEST_x_OP_x(uint32_t, check32, uint64_t, FUNC, SRC, RES, USR_RES) 439 #define TEST_P_OP_P(FUNC, SRC, RES, USR_RES) \ argument 440 TEST_x_OP_x(uint64_t, check64, uint64_t, FUNC, SRC, RES, USR_RES) 442 #define TEST_P_OP_R(FUNC, SRC, RES, USR_RES) \ argument 443 TEST_x_OP_x(uint64_t, check64, uint32_t, FUNC, SRC, RES, USR_RES) [all …]
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/qemu/target/arm/tcg/ |
H A D | translate-neon.c | 809 #define DO_3SAME(INSN, FUNC) \ argument 812 return do_3same(s, a, FUNC); \ 849 #define DO_3SAME_NO_SZ_3(INSN, FUNC) \ argument 855 return do_3same(s, a, FUNC); \ 897 #define WRAP_OOL_FN(WRAPNAME, FUNC) \ argument 901 tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, 0, FUNC); \ 914 #define DO_VQRDMLAH(INSN, FUNC) \ argument 923 return do_3same(s, a, FUNC); \ 929 #define DO_SHA1(NAME, FUNC) \ in DO_VQRDMLAH() argument 930 WRAP_OOL_FN(gen_##NAME##_3s, FUNC) \ in DO_VQRDMLAH() [all …]
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H A D | translate.h | 835 #define TRANS(NAME, FUNC, ...) \ argument 837 { return FUNC(s, __VA_ARGS__); } 838 #define TRANS_FEAT(NAME, FEAT, FUNC, ...) \ argument 840 { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); } 842 #define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...) \ argument 846 return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \
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H A D | vec_helper.c | 1226 #define DO_2OP(NAME, FUNC, TYPE) \ argument 1232 d[i] = FUNC(n[i], stat); \ 1407 #define DO_3OP(NAME, FUNC, TYPE) \ argument 1414 d[i] = FUNC(n[i], m[i], stat); \ 1601 #define DO_MULADD(NAME, FUNC, TYPE) \ argument 1608 d[i] = FUNC(d[i], n[i], m[i], stat); \ 2536 #define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \ argument 2548 d[H(i)] = FUNC(n[H(i * 2)], n[H(i * 2 + 1)], stat); \ 2551 d[H(i + half)] = FUNC(m[H(i * 2)], m[H(i * 2 + 1)], stat); \ 2588 #define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \ argument [all …]
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H A D | translate-sve.c | 3412 #define DO_SVE2_RRX(NAME, FUNC) \ argument 3413 TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \ 3430 #define DO_SVE2_RRX_TB(NAME, FUNC, TOP) \ argument 3431 TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \ 3451 #define DO_SVE2_RRXR(NAME, FUNC) \ argument 3452 TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_arg_zzxz, FUNC, a) 3472 #define DO_SVE2_RRXR_TB(NAME, FUNC, TOP) \ argument 3473 TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC, \ 3508 #define DO_SVE2_RRXR_ROT(NAME, FUNC) \ argument 3509 TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC, \
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H A D | sve_helper.c | 126 #define LOGICAL_PPPP(NAME, FUNC) \ argument 133 d[i] = FUNC(n[i], m[i], g[i]); \ 4216 #define DO_REDUCE(NAME, TYPE, H, FUNC, IDENT) \ argument 4225 return FUNC(lo, hi, status); \
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/qemu/target/loongarch/ |
H A D | translate.h | 13 #define TRANS(NAME, AVAIL, FUNC, ...) \ argument 15 { return avail_##AVAIL(ctx) && FUNC(ctx, a, __VA_ARGS__); }
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/qemu/target/microblaze/ |
H A D | op_helper.c | 447 #define LD_EA(NAME, TYPE, FUNC) \ argument 452 TYPE ret = FUNC(cs->as, ea, MEMTXATTRS_UNSPECIFIED, &txres); \ 466 #define ST_EA(NAME, TYPE, FUNC) \ argument 471 FUNC(cs->as, ea, data, MEMTXATTRS_UNSPECIFIED, &txres); \
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/qemu/target/mips/tcg/ |
H A D | translate.h | 243 #define TRANS(NAME, FUNC, ...) \ argument 245 { return FUNC(ctx, a, __VA_ARGS__); }
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H A D | msa_helper.c | 5274 #define MSA_FN_IMM8(FUNC, DEST, OPERATION) \ argument 5275 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \ 5851 #define MSA_FN_DF(FUNC) \ argument 5852 void helper_msa_##FUNC(CPUMIPSState *env, uint32_t df, uint32_t wd, \
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/qemu/target/hexagon/imported/ |
H A D | alu.idef | 1222 #define VMINORMAX(TAG,STR,FUNC,SHORTTYPE,SETTYPE,GETTYPE,NEL) \ 1228 fSET##SETTYPE(i,RddV,FUNC(fGET##GETTYPE(i,RttV),fGET##GETTYPE(i,RssV))); \ 1232 #define VMINORMAX3(TAG,STR,FUNC,SHORTTYPE,SETTYPE,GETTYPE,NEL) \ 1238 …fSET##SETTYPE(i,RxxV,FUNC(fGET##GETTYPE(i,RxxV),FUNC(fGET##GETTYPE(i,RttV),fGET##GETTYPE(i,RssV)))…
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/qemu/target/ppc/ |
H A D | translate.c | 5681 #define TRANS(NAME, FUNC, ...) \ argument 5683 { return FUNC(ctx, a, __VA_ARGS__); } 5684 #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ argument 5688 return FUNC(ctx, a, __VA_ARGS__); \ 5690 #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ argument 5694 return FUNC(ctx, a, __VA_ARGS__); \ 5697 #define TRANS64(NAME, FUNC, ...) \ argument 5699 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 5700 #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ argument 5705 return FUNC(ctx, a, __VA_ARGS__); \
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/qemu/docs/system/ |
H A D | qemu-block-drivers.rst.inc | 853 # |qemu_system| -drive file=nvme://HOST:BUS:SLOT.FUNC/NAMESPACE 859 |qemu_system| -drive file.driver=nvme,file.device=HOST:BUS:SLOT.FUNC,file.namespace=NAMESPACE 861 *HOST*:*BUS*:*SLOT*.\ *FUNC* is the NVMe controller's PCI device
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/qemu/target/ppc/translate/ |
H A D | vsx-impl.c.inc | 679 #define TCG_OP_IMM_i64(FUNC, OP, IMM) \ 680 static void FUNC(TCGv_i64 t, TCGv_i64 b) \
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/qemu/target/sparc/ |
H A D | translate.c | 2488 #define TRANS(NAME, AVAIL, FUNC, ...) \ argument 2490 { return avail_##AVAIL(dc) && FUNC(dc, __VA_ARGS__); }
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