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Searched refs:FP (Results 1 – 25 of 35) sorted by relevance

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/qemu/disas/
H A Dalpha.c585 #define FP(oo,fff) FP_(oo,fff), FP_MASK macro
901 { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } },
902 { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 },
903 { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 },
904 { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } },
905 { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } },
906 { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 },
907 { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 },
908 { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 },
909 { "sqrtt/m", FP(0x14,0x06B), CIX, ARG_FPZ1 },
[all …]
/qemu/target/arm/tcg/
H A Dsme-fa64.decode56 # --10 110- ---- ---- ---- ---- ---- ---- # Load/store pair of FP registers
57 # --01 1100 ---- ---- ---- ---- ---- ---- # Load FP register (PC-relative literal)
58 # --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register (unscaled imm)
59 # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
60 # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
H A Dm-nocp.decode28 # decoding FP instructions which are in the coprocessor space).
52 # FP system register accesses: these are a special case because accesses
H A Dsve.decode562 # SVE insert SIMD&FP scalar register
627 # SVE conditionally copy element to SIMD&FP scalar
635 # SVE copy element to SIMD&FP scalar register
643 # SVE copy element from SIMD&FP scalar register
968 ### SVE FP Multiply-Add Indexed Group
978 ### SVE FP Multiply Indexed Group
985 ### SVE FP Fast Reduction Group
998 ### SVE FP Compare with Zero Group
1007 ### SVE FP Accumulating Reduction Group
1022 ### SVE FP Arithmetic Predicated Group
[all …]
H A Dmve.decode30 # like Neon FP insns.
34 # FP scalars have size in bit 28, 1 for 16 bit, 0 for 32 bit
771 # 2-operand FP
H A Dneon-dp.decode48 # For FP insns the high bit of 'size' is used as part of opcode decode,
/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_branch.c.inc83 TRANS(bceqz, FP, gen_cz_bc, TCG_COND_EQ)
84 TRANS(bcnez, FP, gen_cz_bc, TCG_COND_NE)
/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc602 /* LOAD FP INTEGER */
1283 /* VECTOR FP ADD */
1285 /* VECTOR FP COMPARE SCALAR */
1287 /* VECTOR FP COMPARE AND SIGNAL SCALAR */
1289 /* VECTOR FP COMPARE EQUAL */
1291 /* VECTOR FP COMPARE HIGH */
1293 /* VECTOR FP COMPARE HIGH OR EQUAL */
1295 /* VECTOR FP CONVERT FROM FIXED 64-BIT */
1297 /* VECTOR FP CONVERT FROM LOGICAL 64-BIT */
1299 /* VECTOR FP CONVERT TO FIXED 64-BIT */
[all …]
/qemu/target/loongarch/
H A Dtranslate.h20 #define avail_FP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP))
H A Dgdbstub.c181 if (FIELD_EX32(env->cpucfg[2], CPUCFG2, FP)) { in loongarch_cpu_register_gdb_regs_for_features()
H A Dmachine.c32 return FIELD_EX64(cpu->env.cpucfg[2], CPUCFG2, FP); in fpu_needed()
H A Dcpu.h143 FIELD(CPUCFG2, FP, 0, 1)
H A Dcpu.c459 data = FIELD_DP32(data, CPUCFG2, FP, 1); in loongarch_la464_initfn()
/qemu/target/hexagon/idef-parser/
H A Didef-parser.lex333 "FP" { yylval->rvalue.type = REGISTER;
H A Dmacros.h.inc98 #define fWRITE_FP(A) (FP = A)
/qemu/target/ppc/
H A Dexcp_helper.c456 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { in powerpc_excp_40x()
567 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { in powerpc_excp_6xx()
708 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { in powerpc_excp_7xx()
858 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { in powerpc_excp_74xx()
1025 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { in powerpc_excp_booke()
1353 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { in powerpc_excp_books()
/qemu/target/hexagon/
H A Dattribs_def.h.inc105 DEF_ATTRIB(IMPLICIT_WRITES_FP, "Writes the frame pointer", "", "UREG.FP")
164 DEF_ATTRIB(NOTE_AXOK, "May only be grouped with ALU32 or non-FP XTYPE.", "", "")
/qemu/target/openrisc/
H A Dinsns.decode176 # FP Instructions
/qemu/target/arm/
H A Dcpu-features.h609 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; in isar_feature_aa64_fp_simd()
615 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; in isar_feature_aa64_fp16()
/qemu/target/hppa/
H A Dinsns.decode459 # FP Fused Multiple-Add
467 # FP operations
/qemu/docs/system/arm/
H A Demulation.rst183 - FP (Floating-point Extension)
/qemu/target/mips/
H A Dcpu-defs.c.inc470 FIXME: Support IEEE 754-2008 FP.
1057 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
/qemu/target/hexagon/imported/
H A Dfloat.idef23 /* Scalar FP */
/qemu/tests/fp/
H A Dwrap.c.inc2 * In this file we wrap QEMU FP functions to look like softfloat/testfloat's,
/qemu/target/loongarch/kvm/
H A Dkvm.c692 if (FIELD_EX32(env->cpucfg[2], CPUCFG2, FP)) { in kvm_check_cpucfg2()

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