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Searched refs:C_O2_I1 (Results 1 – 15 of 15) sorted by relevance

/qemu/tcg/tci/
H A Dtcg-target-con-set.h19 C_O2_I1(r, r, r)
H A Dtcg-target.c.inc1208 TCG_TARGET_REG_BITS == 64 ? C_NotImplemented : C_O2_I1(r, r, r),
/qemu/tcg/mips/
H A Dtcg-target-con-set.h29 C_O2_I1(r, r, r)
H A Dtcg-target.c.inc1445 TCG_TARGET_REG_BITS == 32 ? C_O2_I1(r, r, r) : C_NotImplemented,
/qemu/tcg/aarch64/
H A Dtcg-target-con-set.h38 C_O2_I1(r, r, r)
H A Dtcg-target.c.inc1956 .base.static_constraint = C_O2_I1(r, r, r),
/qemu/tcg/s390x/
H A Dtcg-target-con-set.h44 C_O2_I1(o, m, r)
H A Dtcg-target.c.inc2207 .base.static_constraint = C_O2_I1(o, m, r),
/qemu/tcg/ppc/
H A Dtcg-target-con-set.h41 C_O2_I1(r, r, r)
H A Dtcg-target.c.inc2721 TCG_TARGET_REG_BITS == 64 ? C_N1O1_I1(o, m, r) : C_O2_I1(r, r, r),
/qemu/tcg/arm/
H A Dtcg-target-con-set.h45 C_O2_I1(e, p, q)
H A Dtcg-target.c.inc1653 .base.static_constraint = C_O2_I1(e, p, q),
/qemu/tcg/i386/
H A Dtcg-target-con-set.h57 C_O2_I1(r, r, L)
H A Dtcg-target.c.inc2463 .base.static_constraint = C_O2_I1(r, r, L),
/qemu/tcg/
H A Dtcg.c860 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1), macro
885 #undef C_O2_I1
912 #define C_O2_I1(O1, O2, I1) { 2, 1, { #O1, #O2, #I1 } }, macro
933 #undef C_O2_I1
955 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1) macro