Searched refs:C_O0_I3 (Results 1 – 17 of 17) sorted by relevance
| /qemu/tcg/ppc/ |
| H A D | tcg-target-con-set.h | 16 C_O0_I3(r, r, r)
17 C_O0_I3(o, m, r)
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| H A D | tcg-target.c.inc | 2748 TCG_TARGET_REG_BITS == 64 ? C_O0_I3(o, m, r) : C_O0_I3(r, r, r),
4442 ? C_O0_I3(o, m, r) : C_O0_I3(r, r, r);
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| /qemu/tcg/arm/ |
| H A D | tcg-target-con-set.h | 17 C_O0_I3(q, q, q)
18 C_O0_I3(Q, p, q)
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| H A D | tcg-target.c.inc | 1770 .base.static_constraint = C_O0_I3(Q, p, q),
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| /qemu/tcg/i386/ |
| H A D | tcg-target-con-set.h | 26 C_O0_I3(L, L, L)
27 C_O0_I3(s, L, L)
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| H A D | tcg-target.c.inc | 2625 .base.static_constraint = C_O0_I3(L, L, L),
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| /qemu/tcg/tci/ |
| H A D | tcg-target-con-set.h | 14 C_O0_I3(r, r, r)
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| H A D | tcg-target.c.inc | 1233 TCG_TARGET_REG_BITS == 64 ? C_NotImplemented : C_O0_I3(r, r, r),
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| /qemu/tcg/loongarch64/ |
| H A D | tcg-target-con-set.h | 21 C_O0_I3(r, r, r)
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| H A D | tcg-target.c.inc | 1301 .base.static_constraint = C_O0_I3(r, r, r),
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| /qemu/tcg/mips/ |
| H A D | tcg-target-con-set.h | 15 C_O0_I3(rz, rz, r)
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| H A D | tcg-target.c.inc | 1568 TCG_TARGET_REG_BITS == 32 ? C_O0_I3(rz, rz, r) : C_NotImplemented,
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| /qemu/tcg/aarch64/ |
| H A D | tcg-target-con-set.h | 16 C_O0_I3(rz, rz, r)
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| H A D | tcg-target.c.inc | 1967 .base.static_constraint = C_O0_I3(rz, rz, r),
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| /qemu/tcg/s390x/ |
| H A D | tcg-target-con-set.h | 20 C_O0_I3(o, m, r)
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| H A D | tcg-target.c.inc | 2218 .base.static_constraint = C_O0_I3(o, m, r),
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| /qemu/tcg/ |
| H A D | tcg.c | 848 #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3), macro
876 #undef C_O0_I3
900 #define C_O0_I3(I1, I2, I3) { 0, 3, { #I1, #I2, #I3 } }, macro
924 #undef C_O0_I3
943 #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3) macro
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