Searched refs:required_clk_rate (Results 1 – 1 of 1) sorted by relevance
99 unsigned long rate, required_clk_rate; in tegra_pwm_config() local 139 * required_clk_rate is a reference rate for source clock and in tegra_pwm_config() 141 * source clock rate as required_clk_rate, PWM controller will in tegra_pwm_config() 144 required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH, in tegra_pwm_config() 147 if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate)) in tegra_pwm_config() 149 * required_clk_rate is a lower bound for the input in tegra_pwm_config() 153 * required_clk_rate to get a clock rate that can meet in tegra_pwm_config() 156 required_clk_rate *= 2; in tegra_pwm_config() 158 err = dev_pm_opp_set_rate(pwmchip_parent(chip), required_clk_rate); in tegra_pwm_config() [all...]