Lines Matching refs:required_clk_rate

99 	unsigned long rate, required_clk_rate;
139 		 * required_clk_rate is a reference rate for source clock and
141 		 * source clock rate as required_clk_rate, PWM controller will
144 		required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,
147 		if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))
149 			 * required_clk_rate is a lower bound for the input
153 			 * required_clk_rate to get a clock rate that can meet
156 			required_clk_rate *= 2;
158 		err = dev_pm_opp_set_rate(pwmchip_parent(chip), required_clk_rate);