| /linux/drivers/clk/starfive/ |
| H A D | clk-starfive-jh7110-pll.c | 17 * M: frequency dividing ratio of pre-divider, set by prediv[5:0].
84 unsigned prediv : 6; member
97 unsigned int prediv; member
120 .prediv = JH7110_PLL##_idx##_PREDIV_OFFSET, \
152 u32 prediv; member
164 .prediv = 8,
170 .prediv = 6,
176 .prediv = 24,
182 .prediv = 4,
188 .prediv
[all...] |
| /linux/drivers/clk/mmp/ |
| H A D | clk-audio.c | 120 unsigned int prediv; in audio_pll_recalc_rate() local
137 for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) { in audio_pll_recalc_rate()
138 if (predivs[prediv].parent_rate != parent_rate) in audio_pll_recalc_rate()
147 val |= SSPA_AUD_PLL_CTRL0_FRACT(predivs[prediv].fract); in audio_pll_recalc_rate()
148 val |= SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(predivs[prediv].fbcclk); in audio_pll_recalc_rate()
149 val |= SSPA_AUD_PLL_CTRL0_DIV_MCLK(predivs[prediv].mclk); in audio_pll_recalc_rate()
158 freq = predivs[prediv].freq_vco; in audio_pll_recalc_rate()
170 unsigned int prediv; in audio_pll_round_rate() local
198 unsigned int prediv; audio_pll_set_rate() local
[all...] |
| /linux/drivers/media/dvb-frontends/ |
| H A D | tua6100.c | 62 u32 prediv; in tua6100_set_params() local
105 prediv = (c->frequency * _R_VAL) / (_ri / 1000); in tua6100_set_params()
106 div = prediv / _P_VAL; in tua6100_set_params()
113 reg1[3] |= (prediv - (div*_P_VAL)) & 0x7f; in tua6100_set_params()
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| H A D | dib8000.c | 750 u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ; in dib8000_update_pll() local
754 prediv = reg_1856 & 0x3f; in dib8000_update_pll()
757 if ((pll == NULL) || (pll->pll_prediv == prediv && in dib8000_update_pll()
761 dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio); in dib8000_update_pll()
775 xtal = 2 * (internal / loopdiv) * prediv; in dib8000_update_pll()
791 dprintk("PLL Updated with prediv = %d and loopdiv = %d\n", in dib8000_update_pll()
796 dprintk("PLL: Bandwidth Change %d MHz -> %d MHz (prediv: %d->%d)\n", state->current_demod_bw / 1000, bw / 1000, oldprediv, state->cfg.pll->pll_prediv); in dib8000_update_pll()
799 /** Full PLL change only if prediv is changed **/ in dib8000_update_pll()
802 dprintk("PLL: New Setting for %d MHz Bandwidth (prediv in dib8000_update_pll()
[all...] |
| /linux/drivers/clk/sunxi-ng/ |
| H A D | ccu_mux.c | 21 u16 prediv = 1; in ccu_mux_get_prediv() local
30 return common->prediv; in ccu_mux_get_prediv()
43 prediv = cm->fixed_predivs[i].div; in ccu_mux_get_prediv()
55 prediv = div + 1; in ccu_mux_get_prediv()
59 return prediv; in ccu_mux_get_prediv()
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| H A D | ccu_gate.h | 77 .prediv = _prediv, \
105 .prediv = _prediv, \
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| H A D | ccu_gate.c | 89 rate /= cg->common.prediv; in ccu_gate_recalc_rate()
101 div = cg->common.prediv; in ccu_gate_determine_rate()
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| H A D | ccu-sun6i-rtc.c | 229 .prediv = 750,
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| H A D | ccu-sun5i.c | 90 .prediv = 8,
164 .prediv = 8,
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| H A D | ccu-sun8i-a83t.c | 480 .prediv = 2,
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| /linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-samsung-dcphy.c | 306 u8 prediv; member
1061 S(samsung->pll.scaler) | P(samsung->pll.prediv)); in samsung_mipi_dcphy_pll_configure()
1130 u8 *prediv, u16 *fbdiv, int *dsm, u8 *scaler) in samsung_mipi_dcphy_pll_round_rate() argument
1206 *prediv = best_prediv; in samsung_mipi_dcphy_pll_round_rate()
1409 u16 prediv = samsung->pll.prediv; in samsung_mipi_dcphy_pll_ssc_modulation_calc() local
1416 max_mfr = DIV_ROUND_UP(fin, (20 * prediv) << 5); in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1417 min_mfr = div64_ul(fin, ((150 * prediv) << 5)); in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1457 u8 prediv = 1; in samsung_mipi_dcphy_pll_calc_rate() local
1462 &prediv, in samsung_mipi_dcphy_pll_calc_rate()
[all...] |
| /linux/drivers/clk/pistachio/ |
| H A D | clk-pll.c | 273 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; in pll_gf40lp_frac_recalc_rate() local
276 prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; in pll_gf40lp_frac_recalc_rate()
293 rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24); in pll_gf40lp_frac_recalc_rate()
413 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
417 prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; in pll_gf40lp_laint_recalc_rate()
425 rate = do_div_round_closest(rate, prediv * postdiv1 * postdiv2); in pll_gf40lp_laint_recalc_rate()
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| /linux/drivers/clk/ |
| H A D | clk-vt8500.c | 351 u32 *multiplier, u32 *prediv) in vt8500_find_pll_bits() argument
359 *prediv = 1; in vt8500_find_pll_bits()
363 /* use the prediv to double the resolution */ in vt8500_find_pll_bits()
364 *prediv = 2; in vt8500_find_pll_bits()
366 *prediv = 1; in vt8500_find_pll_bits()
368 *multiplier = rate / (parent_rate / *prediv); in vt8500_find_pll_bits()
369 tclk = (parent_rate / *prediv) * *multiplier; in vt8500_find_pll_bits()
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| H A D | clk-versaclock3.c | 250 unsigned int prediv, premul; in vc3_pfd_recalc_rate() local
254 regmap_read(vc3->regmap, pfd->offs, &prediv); in vc3_pfd_recalc_rate()
257 if (prediv & pfd->mdiv1_bitmsk) { in vc3_pfd_recalc_rate()
264 mdiv = VC3_PLL1_M_DIV(prediv); in vc3_pfd_recalc_rate()
267 if (prediv & pfd->mdiv1_bitmsk) { in vc3_pfd_recalc_rate()
275 mdiv = VC3_PLL2_M_DIV(prediv); in vc3_pfd_recalc_rate()
278 if (prediv & pfd->mdiv1_bitmsk) in vc3_pfd_recalc_rate()
281 mdiv = VC3_PLL3_M_DIV(prediv); in vc3_pfd_recalc_rate()
284 if (prediv & pfd->mdiv2_bitmsk) in vc3_pfd_recalc_rate()
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| H A D | clk-versaclock5.c | 344 unsigned int prediv, div; in vc5_pfd_recalc_rate() local
347 ret = regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv); in vc5_pfd_recalc_rate()
352 if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV) in vc5_pfd_recalc_rate()
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| /linux/drivers/media/i2c/ |
| H A D | tc358746.c | 983 dev_dbg(dev, "Found PLL settings: freq:%lu prediv:%u multi:%u postdiv:%u\n", in tc358746_find_pll_settings()
1112 const unsigned char prediv[] = { 2, 4, 8 }; in tc358746_find_mclk_settings() local
1151 /* First check the prediv */ in tc358746_find_mclk_settings()
1152 for (i = 0; i < ARRAY_SIZE(prediv); i++) { in tc358746_find_mclk_settings()
1153 postdiv = mclkdiv / prediv[i]; in tc358746_find_mclk_settings()
1159 mclk_prediv = prediv[i]; in tc358746_find_mclk_settings()
1161 best_mclk_rate = pll_rate / (prediv[i] * postdiv); in tc358746_find_mclk_settings()
1166 /* No suitable prediv found, so try to adjust the postdiv */ in tc358746_find_mclk_settings()
1193 dev_dbg(dev, "Found MCLK settings: freq:%lu prediv:%u postdiv:%u\n", in tc358746_find_mclk_settings()
1203 unsigned int prediv, postdi in tc358746_recalc_rate() local
[all...] |
| H A D | vgxy61.c | 457 static void compute_pll_parameters_by_freq(u32 freq, u8 *prediv, u8 *mult) in compute_pll_parameters_by_freq() argument
467 *prediv = predivs[i]; in compute_pll_parameters_by_freq()
468 if (freq / *prediv < 12 * HZ_PER_MHZ) in compute_pll_parameters_by_freq()
477 *mult = ((804 * HZ_PER_MHZ) * (*prediv) + freq / 2) / freq; in compute_pll_parameters_by_freq()
1497 u8 prediv, mult; in vgxy61_configure() local
1501 compute_pll_parameters_by_freq(sensor->clk_freq, &prediv, &mult); in vgxy61_configure()
1502 sensor_freq = (mult * sensor->clk_freq) / prediv; in vgxy61_configure()
1513 cci_write(sensor->regmap, VGXY61_REG_CLK_PLL_PREDIV, prediv, &ret); in vgxy61_configure()
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| /linux/drivers/clk/keystone/ |
| H A D | pll.c | 81 u32 mult = 0, prediv, postdiv, val; in clk_pllclk_recalc() local
96 prediv = (val & pll_data->plld_mask); in clk_pllclk_recalc()
109 rate /= (prediv + 1); in clk_pllclk_recalc()
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| /linux/drivers/clk/imx/ |
| H A D | clk-composite-8m.c | 52 int *prediv, int *postdiv) in imx8m_clk_composite_compute_dividers() argument
58 *prediv = 1; in imx8m_clk_composite_compute_dividers()
66 *prediv = div1; in imx8m_clk_composite_compute_dividers()
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| /linux/drivers/clk/ralink/ |
| H A D | clk-mt7621.c | 262 u32 pll, prediv, fbdiv; in mt7621_cpu_recalc_rate() local
279 prediv = FIELD_GET(CPU_PLL_PREDIV_MASK, pll); in mt7621_cpu_recalc_rate()
280 cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv]; in mt7621_cpu_recalc_rate()
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| /linux/drivers/media/usb/dvb-usb/ |
| H A D | dib0700_devices.c | 2035 u8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1; in dib8096p_get_best_sampling() local
2046 adc->pll_prediv = prediv; in dib8096p_get_best_sampling()
2050 /* Find Min and Max prediv */ in dib8096p_get_best_sampling()
2061 deb_info("MIN prediv = %d : MAX prediv = %d", min_prediv, max_prediv); in dib8096p_get_best_sampling()
2065 for (prediv = min_prediv; prediv < max_prediv; prediv++) { in dib8096p_get_best_sampling()
2066 fcp = xtal / prediv; in dib8096p_get_best_sampling()
2069 fmem = ((xtal/prediv) * loopdi in dib8096p_get_best_sampling()
2560 u8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1; dib7090p_get_best_sampling() local
[all...] |
| /linux/drivers/phy/mediatek/ |
| H A D | phy-mtk-hdmi-mt8195.c | 76 static int mtk_hdmi_pll_set_hw(struct clk_hw *hw, u8 prediv, in mtk_hdmi_pll_set_hw() argument
185 prediv_value = ilog2(prediv); in mtk_hdmi_pll_set_hw()
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| /linux/arch/arm64/boot/dts/sprd/ |
| H A D | sc9860.dtsi | 209 aon_prediv: aon-prediv@402d0000 {
210 compatible = "sprd,sc9860-aon-prediv";
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| /linux/drivers/tty/serial/ |
| H A D | sh-sci.c | 2392 unsigned int sr, br, prediv, scrate, c; in sci_scbrr_calc() local
2416 prediv = sr << (2 * c + 1); in sci_scbrr_calc()
2421 * br = freq / (prediv * bps) clamped to [1..256] in sci_scbrr_calc()
2422 * err = freq / (br * prediv) - bps in sci_scbrr_calc()
2427 if (bps > UINT_MAX / prediv) in sci_scbrr_calc()
2430 scrate = prediv * bps; in sci_scbrr_calc()
2434 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; in sci_scbrr_calc()
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