| /linux/drivers/clk/socfpga/ |
| H A D | clk-gate-a10.c | 45 u32 clk_gate[2]; in __socfpga_gate_init() local
59 rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2); in __socfpga_gate_init()
61 clk_gate[0] = 0; in __socfpga_gate_init()
63 if (clk_gate[0]) { in __socfpga_gate_init()
64 socfpga_clk->hw.reg = clk_mgr_a10_base_addr + clk_gate[0]; in __socfpga_gate_init()
65 socfpga_clk->hw.bit_idx = clk_gate[1]; in __socfpga_gate_init()
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| H A D | clk.h | 40 struct clk_gate hw;
44 struct clk_gate hw;
56 struct clk_gate hw;
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| /linux/drivers/clk/ralink/ |
| H A D | clk-mt7621.c | 100 struct mt7621_gate *clk_gate = to_mt7621_gate(hw); in mt7621_gate_enable() local
101 struct regmap *sysc = clk_gate->priv->sysc; in mt7621_gate_enable()
104 clk_gate->bit_idx, clk_gate->bit_idx); in mt7621_gate_enable()
109 struct mt7621_gate *clk_gate = to_mt7621_gate(hw); in mt7621_gate_disable() local
110 struct regmap *sysc = clk_gate->priv->sysc; in mt7621_gate_disable()
112 regmap_update_bits(sysc, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0); in mt7621_gate_disable()
117 struct mt7621_gate *clk_gate = to_mt7621_gate(hw); in mt7621_gate_is_enabled() local
118 struct regmap *sysc = clk_gate->priv->sysc; in mt7621_gate_is_enabled()
124 return val & clk_gate in mt7621_gate_is_enabled()
[all...] |
| /linux/drivers/clk/imx/ |
| H A D | clk-gate-exclusive.c | 20 * The imx exclusive gate clock is a subclass of basic clk_gate
25 struct clk_gate gate;
31 struct clk_gate *gate = to_clk_gate(hw); in clk_gate_exclusive_enable()
62 struct clk_gate *gate; in imx_clk_hw_gate_exclusive()
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| H A D | clk-composite-7ulp.c | 30 struct clk_gate *gate = to_clk_gate(hw); in pcc_gate_enable()
77 struct clk_gate *gate = NULL; in imx_ulp_clk_hw_composite()
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| H A D | clk-composite-8m.c | 193 struct clk_gate *gate = to_clk_gate(hw); in imx8m_clk_composite_gate_enable()
228 struct clk_gate *gate = NULL; in __imx8m_clk_hw_composite()
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| /linux/drivers/clk/sunxi/ |
| H A D | clk-a10-hosc.c | 21 struct clk_gate *gate; in sun4i_osc_clk_setup()
32 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); in sun4i_osc_clk_setup()
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| H A D | clk-a20-gmac.c | 57 struct clk_gate *gate; in sun7i_a20_gmac_clk_setup()
70 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); in sun7i_a20_gmac_clk_setup()
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| H A D | clk-a10-pll2.c | 45 struct clk_gate *gate; in sun4i_pll2_setup()
74 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); in sun4i_pll2_setup()
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| H A D | clk-factors.h | 51 struct clk_gate *gate;
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| H A D | clk-a10-mod1.c | 25 struct clk_gate *gate; in sun4i_mod1_clk_setup()
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| H A D | clk-sun4i-pll3.c | 25 struct clk_gate *gate; in sun4i_a10_pll3_setup()
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| H A D | clk-factors.c | 183 struct clk_gate *gate = NULL; in __sunxi_factors_register()
216 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); in __sunxi_factors_register()
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| H A D | clk-sun8i-mbus.c | 31 struct clk_gate *gate; in sun8i_a23_mbus_setup()
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| /linux/drivers/clk/renesas/ |
| H A D | rcar-cpg-lib.c | 128 struct clk_gate gate;
178 struct clk_gate gate;
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| H A D | rcar-gen2-cpg.c | 169 struct clk_gate *gate; in cpg_rcan_clk_register()
213 struct clk_gate *gate; in cpg_adsp_clk_register()
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| /linux/drivers/clk/st/ |
| H A D | clk-flexgen.c | 37 struct clk_gate pgate;
41 struct clk_gate fgate;
45 struct clk_gate sync;
51 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
162 struct clk_gate *config = to_clk_gate(sync_hw); in flexgen_set_rate()
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| /linux/drivers/clk/ |
| H A D | clk-stm32f4.c | 540 struct clk_gate gate;
636 struct clk_gate *gate = to_clk_gate(hw); in stm32f4_pll_enable()
662 struct clk_gate *gate = to_clk_gate(hw); in stm32f4_pll_recalc()
676 struct clk_gate *gate = to_clk_gate(hw); in stm32f4_pll_round_rate()
693 struct clk_gate *gate = to_clk_gate(hw); in stm32f4_pll_set_ssc()
719 struct clk_gate *gate = to_clk_gate(hw); in stm32f4_pll_set_rate()
849 struct clk_gate *gate = to_clk_gate(hw); in stm32f4_pll_init_ssc()
1048 struct clk_gate gate;
1056 struct clk_gate *gate = to_clk_gate(hw); in rgclk_enable()
1198 struct clk_gate *gat in stm32_register_cclk()
[all...] |
| H A D | clk-fsl-sai.c | 25 struct clk_gate gate;
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| /linux/drivers/clk/nxp/ |
| H A D | clk-lpc18xx-ccu.c | 40 struct clk_gate gate;
136 struct clk_gate *gate = to_clk_gate(hw); in lpc18xx_ccu_gate_endisable()
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| H A D | clk-lpc18xx-cgu.c | 166 struct clk_gate gate;
200 struct clk_gate gate;
263 struct clk_gate gate;
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| /linux/drivers/clk/mmp/ |
| H A D | clk-audio.c | 69 struct clk_gate sysclk_gate;
70 struct clk_gate sspa0_gate;
71 struct clk_gate sspa1_gate;
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| /linux/drivers/iio/adc/ |
| H A D | meson_saradc.c | 350 struct clk_gate clk_gate; member
775 priv->clk_gate.reg = base + MESON_SAR_ADC_REG3; in meson_sar_adc_clk_init()
776 priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN); in meson_sar_adc_clk_init()
777 priv->clk_gate.hw.init = &init; in meson_sar_adc_clk_init()
779 priv->adc_clk = devm_clk_register(dev, &priv->clk_gate.hw); in meson_sar_adc_clk_init()
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| /linux/drivers/media/platform/verisilicon/ |
| H A D | hantro_postproc.c | 41 .clk_gate = {G1_REG_PP_DEV_CONFIG, 1, 0x1},
95 HANTRO_PP_REG_WRITE(vpu, clk_gate, 0x1); in hantro_postproc_g1_enable()
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| /linux/Documentation/driver-api/ |
| H A D | clk.rst | 111 struct clk_gate {
118 struct clk_gate contains struct clk_hw hw as well as hardware-specific
143 static void clk_gate_set_bit(struct clk_gate *gate)
154 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
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