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Searched refs:MDIO_MMD_VEND1 (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/net/phy/
H A Dnxp-c45-tja11xx.c393 ts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
395 ts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
397 ts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
399 ts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
424 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_0, in _nxp_c45_ptp_settime64()
426 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_1, in _nxp_c45_ptp_settime64()
428 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_0, in _nxp_c45_ptp_settime64()
430 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_1, in _nxp_c45_ptp_settime64()
464 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_adjfine()
472 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_adjfine()
[all …]
H A Dmicrochip_t1.c314 { "TX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG0, 14},
315 { "RX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG1, 14},
316 { "RX ERR Count detected by PCS", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG3, 16},
317 { "TX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG4, 8},
318 { "RX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG5, 8},
319 { "RX ERR Count for SGMII MII2GMII", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG6, 8},
1094 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in lan887x_rgmii_init()
1101 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0, in lan887x_rgmii_init()
1108 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in lan887x_rgmii_init()
1118 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in lan887x_rgmii_init()
[all...]
H A Das21xxx.c303 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLB_REG_CPU_CTRL, in aeon_firmware_boot()
308 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_FW_START_ADDR, in aeon_firmware_boot()
313 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, in aeon_firmware_boot()
319 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, in aeon_firmware_boot()
330 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, in aeon_firmware_boot()
336 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, in aeon_firmware_boot()
342 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, in aeon_firmware_boot()
348 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLB_REG_CPU_CTRL, in aeon_firmware_boot()
400 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, VEND1_IPC_STS, val, in aeon_ipc_wait_cmd()
423 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_CM in aeon_ipc_send_cmd()
[all...]
H A Dmxl-gpy.c190 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA); in gpy_hwmon_read()
259 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO, in gpy_mbox_read()
267 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd); in gpy_mbox_read()
276 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, in gpy_mbox_read()
283 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA); in gpy_mbox_read()
377 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, in gpy_2500basex_chk()
386 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL); in gpy_sgmii_aneg_en()
504 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, in gpy_config_aneg()
551 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, in gpy_update_interface()
569 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTR in gpy_update_interface()
[all...]
H A Dteranetics.c39 if (!phy_read_mmd(phydev, MDIO_MMD_VEND1, 93)) in teranetics_aneg_done()
54 if (!phy_read_mmd(phydev, MDIO_MMD_VEND1, 93)) { in teranetics_read_status()
H A Dadin1100.c198 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, in adin_set_powerdown_mode()
203 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret, in adin_set_powerdown_mode()
236 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN); in adin_soft_reset()
240 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret, in adin_soft_reset()
H A Dair_en8811h.c54 /* Registers on MDIO_MMD_VEND1 */
451 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, in en8811h_wait_mcu_ready()
989 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_1, in en8811h_config_init()
993 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_2, in en8811h_config_init()
997 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, in en8811h_config_init()
1001 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, in en8811h_config_init()
1145 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, in en8811h_clear_intr()
1150 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, in en8811h_clear_intr()
H A Dbcm84881.c209 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x4011); in bcm84881_read_status()
H A Dphy_device.c955 if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) { in get_phy_c45_ids()
997 if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) { in get_phy_c45_ids()
H A Dnxp-c45-tja11xx-macsec.c1612 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES, in nxp_c45_macsec_config_init()
/linux/drivers/net/phy/mediatek/
H A Dmtk-ge-soc.c142 /* Registers on MDIO_MMD_VEND1 */
394 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, in cal_cycle()
397 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, in cal_cycle()
407 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, in cal_cycle()
409 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP); in cal_cycle()
420 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, in rext_fill_result()
441 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, in tx_offset_fill_result()
443 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, in tx_offset_fill_result()
445 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, in tx_offset_fill_result()
447 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_ in tx_offset_fill_result()
[all...]
H A Dmtk-ge.c21 /* Registers on MDIO_MMD_VEND1 */
49 phy_modify_mmd(phydev, MDIO_MMD_VEND1, in mtk_gephy_config_init()
59 phy_modify_mmd(phydev, MDIO_MMD_VEND1, in mtk_gephy_config_init()
82 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, in mt7531_phy_config_init()
87 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_GBE_MODE_TX_DELAY_SEL, in mt7531_phy_config_init()
91 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TEST_MODE_TX_DELAY_SEL, in mt7531_phy_config_init()
H A Dmtk-2p5ge.c31 /* Registers on MDIO_MMD_VEND1 */
88 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD1, 0x1100); in mt798x_2p5ge_phy_load_fw()
89 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD2, 0x00df); in mt798x_2p5ge_phy_load_fw()
124 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL, in mt798x_2p5ge_phy_config_init()
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Daq100x.c71 int err = t3_phy_reset(phy, MDIO_MMD_VEND1, 3000); in aq100x_reset()
86 err = t3_mdio_write(phy, MDIO_MMD_VEND1, AQ_IMASK_GLOBAL, IMASK_GLOBAL); in aq100x_intr_enable()
92 return t3_mdio_write(phy, MDIO_MMD_VEND1, AQ_IMASK_GLOBAL, 0); in aq100x_intr_disable()
99 t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_IFLAG_GLOBAL, &v); in aq100x_intr_clear()
110 err = t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_IFLAG_GLOBAL, &cause); in aq100x_intr_handler()
292 err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v); in t3_aq100x_phy_prep()
319 t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_FW_VERSION, &v); in t3_aq100x_phy_prep()
328 err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v); in t3_aq100x_phy_prep()
332 err = t3_mdio_change_bits(phy, MDIO_MMD_VEND1, MDIO_CTRL1, in t3_aq100x_phy_prep()
/linux/drivers/net/ethernet/aquantia/atlantic/macsec/
H A Dmacsec_api.c83 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
86 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
94 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
97 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
108 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
111 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, MSS_INGRESS_LUT_CTL_REGISTER_ADDR, in set_raw_ingress_record()
137 ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in get_raw_ingress_record()
142 ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in get_raw_ingress_record()
151 ret = aq_mss_mdio_read(hw, MDIO_MMD_VEND1, in get_raw_ingress_record()
157 ret = aq_mss_mdio_read(hw, MDIO_MMD_VEND1, in get_raw_ingress_record()
[all...]
/linux/drivers/net/phy/aquantia/
H A Daquantia_leds.c17 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index), in aqr_phy_led_brightness_set()
55 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index)); in aqr_phy_led_hw_control_get()
113 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index), in aqr_phy_led_hw_control_set()
122 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_DRIVE(index), in aqr_phy_led_active_low_set()
H A Daquantia_hwmon.c44 int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg); in aqr_hwmon_get()
65 return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp); in aqr_hwmon_set()
70 int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg); in aqr_hwmon_test_bit()
/linux/drivers/net/dsa/mv88e6xxx/
H A Dpcs-639x.c680 { MDIO_MMD_VEND1, 0x8093, 0xcb5a, 0xffff }, in mv88e6393x_erratum_5_2()
681 { MDIO_MMD_VEND1, 0x8171, 0x7088, 0xffff }, in mv88e6393x_erratum_5_2()
682 { MDIO_MMD_VEND1, 0x80c9, 0x311a, 0xffff }, in mv88e6393x_erratum_5_2()
683 { MDIO_MMD_VEND1, 0x80a2, 0x8000, 0xff7f }, in mv88e6393x_erratum_5_2()
684 { MDIO_MMD_VEND1, 0x80a9, 0x0000, 0xfff0 }, in mv88e6393x_erratum_5_2()
685 { MDIO_MMD_VEND1, 0x80a3, 0x0000, 0xf8ff }, in mv88e6393x_erratum_5_2()
736 return mdiodev_c45_write(&mpcs->mdio, MDIO_MMD_VEND1, 0x8000, 0x58); in mv88e6393x_fix_2500basex_an()
/linux/drivers/net/ethernet/aquantia/atlantic/
H A Daq_phy.c165 val = aq_phy_read_reg(aq_hw, MDIO_MMD_VEND1, in aq_phy_disable_ptp()
168 aq_phy_write_reg(aq_hw, MDIO_MMD_VEND1, in aq_phy_disable_ptp()
/linux/include/uapi/linux/
H A Dmdio.h28 #define MDIO_MMD_VEND1 30 /* Vendor specific 1 */ macro
160 #define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
/linux/drivers/net/phy/realtek/
H A Drealtek_main.c1076 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); in rtl822xb_config_init()
1080 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, in rtl822xb_config_init()
1087 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); in rtl822xb_config_init()
1091 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); in rtl822xb_config_init()
1095 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); in rtl822xb_config_init()
1107 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); in rtl822xb_get_rate_matching()
1163 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); in rtl822xb_update_interface()
/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_x550.c2341 MDIO_MMD_VEND1, in ixgbe_get_lasi_ext_t_x550em()
2349 MDIO_MMD_VEND1, in ixgbe_get_lasi_ext_t_x550em()
2358 MDIO_MMD_VEND1, in ixgbe_get_lasi_ext_t_x550em()
2374 MDIO_MMD_VEND1, in ixgbe_get_lasi_ext_t_x550em()
2455 MDIO_MMD_VEND1, in ixgbe_enable_lasi_ext_t_x550em()
2464 MDIO_MMD_VEND1, in ixgbe_enable_lasi_ext_t_x550em()
2471 MDIO_MMD_VEND1, in ixgbe_enable_lasi_ext_t_x550em()
2480 MDIO_MMD_VEND1, in ixgbe_enable_lasi_ext_t_x550em()
2487 MDIO_MMD_VEND1, in ixgbe_enable_lasi_ext_t_x550em()
2495 MDIO_MMD_VEND1, in ixgbe_enable_lasi_ext_t_x550em()
[all...]
H A Dixgbe_phy.c1303 MDIO_MMD_VEND1, in ixgbe_check_phy_link_tnx()
2809 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, &reg); in ixgbe_set_copper_phy_power()
2821 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg); in ixgbe_set_copper_phy_power()
/linux/drivers/net/ethernet/microchip/
H A Dlan743x_ethtool.c1237 { ETH_SR_VSMMD_DEV_ID1, MDIO_MMD_VEND1, 0x0002}, in lan743x_sgmii_regs()
1238 { ETH_SR_VSMMD_DEV_ID2, MDIO_MMD_VEND1, 0x0003}, in lan743x_sgmii_regs()
1239 { ETH_SR_VSMMD_PCS_ID1, MDIO_MMD_VEND1, 0x0004}, in lan743x_sgmii_regs()
1240 { ETH_SR_VSMMD_PCS_ID2, MDIO_MMD_VEND1, 0x0005}, in lan743x_sgmii_regs()
1241 { ETH_SR_VSMMD_STS, MDIO_MMD_VEND1, 0x0008}, in lan743x_sgmii_regs()
1242 { ETH_SR_VSMMD_CTRL, MDIO_MMD_VEND1, 0x0009}, in lan743x_sgmii_regs()
/linux/rust/kernel/net/phy/
H A Dreg.rs171 pub const VEND1: Self = Mmd(uapi::MDIO_MMD_VEND1 as u8);