Lines Matching refs:MDIO_MMD_VEND1
314 { "TX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG0, 14},
315 { "RX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG1, 14},
316 { "RX ERR Count detected by PCS", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG3, 16},
317 { "TX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG4, 8},
318 { "RX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG5, 8},
319 { "RX ERR Count for SGMII MII2GMII", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG6, 8},
1094 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1101 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
1108 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1118 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1128 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1135 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
1144 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
1150 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SGMII_PCS_CFG,
1165 txc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0);
1170 rxc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1);
1206 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1,
1212 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0,
1223 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_EFUSE_READ_DAT9);
1286 priv->clock = mchp_rds_ptp_probe(phydev, MDIO_MMD_VEND1,
1293 phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1305 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1314 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1351 {MDIO_MMD_VEND1, LAN887x_CDR_CONFIG1_100, 0x0ab1},
1352 {MDIO_MMD_VEND1, LAN887x_LOCK1_EQLSR_CONFIG_100, 0x5274},
1353 {MDIO_MMD_VEND1, LAN887x_SLV_HD_MUFAC_CONFIG_100, 0x0d74},
1354 {MDIO_MMD_VEND1, LAN887x_PLOCK_MUFAC_CONFIG_100, 0x0aea},
1355 {MDIO_MMD_VEND1, LAN887x_PROT_DISABLE_100, 0x0360},
1356 {MDIO_MMD_VEND1, LAN887x_KF_LOOP_SAT_CONFIG_100, 0x0c30},
1358 {MDIO_MMD_VEND1, LAN887X_LOCK1_EQLSR_CONFIG, 0x2a78},
1359 {MDIO_MMD_VEND1, LAN887X_LOCK3_EQLSR_CONFIG, 0x1368},
1360 {MDIO_MMD_VEND1, LAN887X_PROT_DISABLE, 0x1354},
1361 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN6, 0x3C84},
1362 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN7, 0x3ca5},
1363 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN8, 0x3ca5},
1364 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN9, 0x3ca5},
1365 {MDIO_MMD_VEND1, LAN887X_ECHO_DELAY_CONFIG, 0x0024},
1366 {MDIO_MMD_VEND1, LAN887X_FFE_MAX_CONFIG, 0x227f},
1385 {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x000f},
1392 {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x0014},
1400 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
1447 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
1453 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_SOFT_RST,
1557 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS);
1562 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_MSK,
1565 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_MSK,
1570 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS);
1592 irq_status = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS);
1616 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_HARD_RST,
1655 {MDIO_MMD_VEND1, LAN887X_MAX_PGA_GAIN_100, 0x1f},
1656 {MDIO_MMD_VEND1, LAN887X_MIN_PGA_GAIN_100, 0x0},
1657 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_TDR_THRESH_100, 0x1},
1658 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_AGC_THRESH_100, 0x3c},
1659 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MIN_WAIT_CONFIG_100, 0x0},
1660 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100, 0x46},
1661 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_CYC_CONFIG_100, 0x5a},
1662 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_TX_PULSE_CONFIG_100, 0x44d5},
1663 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MIN_PGA_GAIN_100, 0x0},
1684 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1714 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
1727 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
1744 rc = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
1752 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1762 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
1799 gain_idx = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1806 pos_peak = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1813 neg_peak = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1820 pos_peak_time = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1827 neg_peak_time = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1880 gain_idx_hybrid = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1887 pos_peak_time_hybrid = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1933 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
1983 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1,
1989 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SQI_CONFIG_100,
1994 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SQI_CONFIG_100);
1998 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_POKE_PEEK_100,
2019 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1,
2025 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
2086 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
2093 rc = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
2101 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_DCQ_SQI_STATUS);