| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | pppcielanes.c | 56 uint8_t encode_pcie_lane_width(uint32_t num_lanes) in encode_pcie_lane_width() argument
58 return pp_r600_encode_lanes[num_lanes]; in encode_pcie_lane_width()
61 uint8_t decode_pcie_lane_width(uint32_t num_lanes) in decode_pcie_lane_width() argument
63 return pp_r600_decoded_lanes[num_lanes]; in decode_pcie_lane_width()
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| H A D | pppcielanes.h | 27 extern uint8_t encode_pcie_lane_width(uint32_t num_lanes);
28 extern uint8_t decode_pcie_lane_width(uint32_t num_lanes);
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| /linux/drivers/media/i2c/adv748x/ |
| H A D | adv748x-core.c | 367 tx->active_lanes = min(tx->num_lanes, 2U); in adv748x_link_setup()
380 tx->active_lanes = tx->num_lanes; in adv748x_link_setup()
613 unsigned int num_lanes; in adv748x_parse_csi2_lanes() local
623 num_lanes = vep.bus.mipi_csi2.num_data_lanes; in adv748x_parse_csi2_lanes()
626 if (num_lanes != 1 && num_lanes != 2 && num_lanes != 4) { in adv748x_parse_csi2_lanes()
628 num_lanes); in adv748x_parse_csi2_lanes()
632 state->txa.num_lanes = num_lanes; in adv748x_parse_csi2_lanes()
[all...] |
| /linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-snps-pcie3.c | 67 int num_lanes; member
106 for (int i = 0; i < priv->num_lanes; i++) { in rockchip_p3phy_rk3568_init()
164 for (int i = 0; i < priv->num_lanes; i++) { in rockchip_p3phy_rk3588_init()
284 priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes", in rockchip_p3phy_probe()
289 if (priv->num_lanes == -EINVAL) { in rockchip_p3phy_probe()
291 priv->num_lanes = 1; in rockchip_p3phy_probe()
293 } else if (priv->num_lanes < 0) { in rockchip_p3phy_probe()
294 dev_err(dev, "failed to read data-lanes property %d\n", priv->num_lanes); in rockchip_p3phy_probe()
295 return priv->num_lanes; in rockchip_p3phy_probe()
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| H A D | phy-rockchip-usbdp.c | 881 int ret, i, num_lanes; in rk_udphy_parse_lane_mux_data() local
883 num_lanes = device_property_count_u32(udphy->dev, "rockchip,dp-lane-mux"); in rk_udphy_parse_lane_mux_data()
884 if (num_lanes < 0) { in rk_udphy_parse_lane_mux_data()
890 if (num_lanes != 2 && num_lanes != 4) in rk_udphy_parse_lane_mux_data()
895 udphy->dp_lane_sel, num_lanes); in rk_udphy_parse_lane_mux_data()
899 for (i = 0; i < num_lanes; i++) { in rk_udphy_parse_lane_mux_data()
908 for (j = i + 1; j < num_lanes; j++) { in rk_udphy_parse_lane_mux_data()
916 if (num_lanes == 2) { in rk_udphy_parse_lane_mux_data()
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| /linux/drivers/pci/controller/dwc/ |
| H A D | pci-keystone.c | 128 int num_lanes; member
989 int num_lanes = ks_pcie->num_lanes; in ks_pcie_disable_phy() local
991 while (num_lanes--) { in ks_pcie_disable_phy()
992 phy_power_off(ks_pcie->phy[num_lanes]); in ks_pcie_disable_phy()
993 phy_exit(ks_pcie->phy[num_lanes]); in ks_pcie_disable_phy()
1001 int num_lanes = ks_pcie->num_lanes; in ks_pcie_enable_phy() local
1003 for (i = 0; i < num_lanes; i++) { in ks_pcie_enable_phy()
1155 u32 num_lanes; in ks_pcie_probe() local
1365 int num_lanes = ks_pcie->num_lanes; ks_pcie_remove() local
[all...] |
| /linux/drivers/phy/ti/ |
| H A D | phy-j721e-wiz.c | 385 u32 num_lanes; member
417 u32 num_lanes = wiz->num_lanes; in wiz_p_mac_div_sel() local
421 for (i = 0; i < num_lanes; i++) { in wiz_p_mac_div_sel()
440 u32 num_lanes = wiz->num_lanes; in wiz_mode_select() local
445 for (i = 0; i < num_lanes; i++) { in wiz_mode_select()
469 u32 num_lanes = wiz->num_lanes; in wiz_init_raw_interface() local
473 for (i = 0; i < num_lanes; in wiz_init_raw_interface()
522 int num_lanes = wiz->num_lanes; wiz_regfield_init() local
1276 u32 num_lanes = wiz->num_lanes; wiz_phy_reset_deassert() local
1416 u32 reg, num_lanes = 1, phy_type = PHY_NONE; wiz_get_lane_phy_types() local
1458 u32 num_lanes; wiz_probe() local
[all...] |
| /linux/drivers/gpu/drm/bridge/adv7511/ |
| H A D | adv7533.c | 164 u32 num_lanes; in adv7533_parse_dt() local
166 of_property_read_u32(np, "adi,dsi-lanes", &num_lanes); in adv7533_parse_dt()
168 if (num_lanes < 2 || num_lanes > 4) in adv7533_parse_dt()
171 adv->num_dsi_lanes = num_lanes; in adv7533_parse_dt()
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| /linux/drivers/acpi/ |
| H A D | mipi-disco-img.c | 492 int num_lanes = 0; in init_csi2_port() local
509 num_lanes = ret; in init_csi2_port()
511 if (num_lanes > ACPI_DEVICE_CSI2_DATA_LANES) { in init_csi2_port()
513 num_lanes); in init_csi2_port()
514 num_lanes = ACPI_DEVICE_CSI2_DATA_LANES; in init_csi2_port()
519 val, num_lanes); in init_csi2_port()
523 for (i = 0; i < num_lanes; i++) in init_csi2_port()
529 num_lanes); in init_csi2_port()
536 } else if (ret * BITS_PER_TYPE(u8) < num_lanes + 1) { in init_csi2_port()
538 ret * BITS_PER_TYPE(u8), num_lanes in init_csi2_port()
[all...] |
| /linux/drivers/phy/mediatek/ |
| H A D | phy-mtk-pcie.c | 51 * @num_lanes: supported lane numbers
55 int num_lanes; member
122 for (i = 0; i < pcie_phy->data->num_lanes; i++) in mtk_pcie_phy_init()
184 pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes * in mtk_pcie_read_efuse()
189 for (i = 0; i < pcie_phy->data->num_lanes; i++) { in mtk_pcie_read_efuse()
245 .num_lanes = 2,
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| H A D | phy-mtk-mipi-csi-0-5.c | 30 u32 num_lanes; member
184 if (priv->num_lanes != 4) { in mtk_mipi_cdphy_xlate()
231 ret = of_property_read_u32(dev->of_node, "num-lanes", &port->num_lanes); in mtk_mipi_cdphy_probe()
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| /linux/drivers/nvdimm/ |
| H A D | region.c | 24 if (nd_region->num_lanes > num_online_cpus() in nd_region_probe()
25 && nd_region->num_lanes < num_possible_cpus() in nd_region_probe()
28 num_online_cpus(), nd_region->num_lanes, in nd_region_probe()
31 nd_region->num_lanes); in nd_region_probe()
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| /linux/drivers/gpu/drm/bridge/cadence/ |
| H A D | cdns-mhdp8546-core.c | 563 values[1] = link->num_lanes; in cdns_mhdp_link_configure()
826 CDNS_DP_LANE_EN_LANES(mhdp->link.num_lanes)); in cdns_mhdp_link_training_init()
830 phy_cfg.dp.lanes = mhdp->link.num_lanes; in cdns_mhdp_link_training_init()
871 for (i = 0; i < mhdp->link.num_lanes; i++) { in cdns_mhdp_get_adjust_train()
936 for (i = 0; i < mhdp->link.num_lanes; i++) { in cdns_mhdp_adjust_requested_eq()
959 for (i = 0; i < mhdp->link.num_lanes; i++) { in cdns_mhdp_print_lt_status()
969 mhdp->link.num_lanes, mhdp->link.rate / 100, in cdns_mhdp_print_lt_status()
1002 phy_cfg.dp.lanes = mhdp->link.num_lanes; in cdns_mhdp_link_training_channel_eq()
1014 cdns_mhdp_adjust_lt(mhdp, mhdp->link.num_lanes, in cdns_mhdp_link_training_channel_eq()
1017 r = drm_dp_clock_recovery_ok(link_status, mhdp->link.num_lanes); in cdns_mhdp_link_training_channel_eq()
[all...] |
| /linux/drivers/iio/adc/ |
| H A D | ad4080.c | 181 unsigned int num_lanes; member
479 ret = iio_backend_num_lanes_set(st->back, st->num_lanes); in ad4080_setup()
495 if (st->num_lanes > 1) { in ad4080_setup()
517 st->num_lanes = 1; in ad4080_properties_parse()
518 device_property_read_u32(dev, "adi,num-lanes", &st->num_lanes); in ad4080_properties_parse()
519 if (!st->num_lanes || st->num_lanes > 2) in ad4080_properties_parse()
522 st->num_lanes); in ad4080_properties_parse()
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| /linux/drivers/media/platform/cadence/ |
| H A D | cdns-csi2rx.c | 136 u8 num_lanes; member
278 fmt->bpp, 2 * csi2rx->num_lanes); in csi2rx_configure_ext_dphy()
283 csi2rx->num_lanes, cfg); in csi2rx_configure_ext_dphy()
317 reg = csi2rx->num_lanes << 8; in csi2rx_start()
318 for (i = 0; i < csi2rx->num_lanes; i++) { in csi2rx_start()
329 for (i = csi2rx->num_lanes; i < csi2rx->max_lanes; i++) { in csi2rx_start()
341 for (i = 0; i < csi2rx->num_lanes; i++) { in csi2rx_start()
755 csi2rx->num_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; in csi2rx_parse_dt()
756 if (csi2rx->num_lanes > csi2rx->max_lanes) { in csi2rx_parse_dt()
758 csi2rx->num_lanes); in csi2rx_parse_dt()
[all...] |
| H A D | cdns-csi2tx.c | 116 unsigned int num_lanes; member
251 for (i = 0; i < csi2tx->num_lanes; i++) in csi2tx_dphy_init_finish()
273 for (i = 0; i < csi2tx->num_lanes; i++) in csi2tx_dphy_setup()
519 csi2tx->num_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; in csi2tx_check_lanes()
520 if (csi2tx->num_lanes > csi2tx->max_lanes) { in csi2tx_check_lanes()
527 for (i = 0; i < csi2tx->num_lanes; i++) { in csi2tx_check_lanes()
627 csi2tx->num_lanes, csi2tx->max_lanes, csi2tx->max_streams, in csi2tx_probe()
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| /linux/drivers/gpu/drm/msm/dp/ |
| H A D | dp_panel.c | 109 link_info->num_lanes = drm_dp_max_lane_count(dpcd); in msm_dp_panel_read_dpcd()
112 if (link_info->num_lanes > msm_dp_panel->max_dp_lanes) in msm_dp_panel_read_dpcd()
113 link_info->num_lanes = msm_dp_panel->max_dp_lanes; in msm_dp_panel_read_dpcd()
121 if (max_lttpr_lanes && max_lttpr_lanes < link_info->num_lanes) in msm_dp_panel_read_dpcd()
122 link_info->num_lanes = max_lttpr_lanes; in msm_dp_panel_read_dpcd()
131 drm_dbg_dp(panel->drm_dev, "lane_count=%d\n", link_info->num_lanes); in msm_dp_panel_read_dpcd()
151 data_rate_khz = link_info->num_lanes * link_info->rate * 8; in msm_dp_panel_get_supported_bpp()
187 !is_lane_count_valid(msm_dp_panel->link_info.num_lanes) || in msm_dp_panel_read_sink_caps()
190 msm_dp_panel->link_info.num_lanes); in msm_dp_panel_read_sink_caps()
|
| H A D | dp_ctrl.c | 182 values[1] = link->num_lanes; in msm_dp_aux_link_configure()
404 config |= ((ctrl->link->link_params.num_lanes - 1) in msm_dp_ctrl_config_ctrl()
1243 in.nlanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_calc_tu_parameters()
1346 lane_cnt = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_update_phy_vx_px()
1449 ctrl->link->link_params.num_lanes)) { in msm_dp_ctrl_link_train_1()
1505 if (ctrl->link->link_params.num_lanes == 1) in msm_dp_ctrl_link_lane_down_shift()
1508 ctrl->link->link_params.num_lanes /= 2; in msm_dp_ctrl_link_lane_down_shift()
1571 ctrl->link->link_params.num_lanes)) { in msm_dp_ctrl_link_train_2()
1619 link_info.num_lanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_link_train()
2254 int num_lanes = ctrl->link->link_params.num_lanes; msm_dp_ctrl_channel_eq_ok() local
[all...] |
| /linux/drivers/pci/controller/cadence/ |
| H A D | pci-j721e.c | 60 u32 num_lanes; member
220 u32 lanes = pcie->num_lanes; in j721e_pcie_set_lane_count()
457 u32 num_lanes; in j721e_pcie_probe() local
526 ret = of_property_read_u32(node, "num-lanes", &num_lanes); in j721e_pcie_probe()
527 if (ret || num_lanes > data->max_lanes) { in j721e_pcie_probe()
529 num_lanes = 1; in j721e_pcie_probe()
532 pcie->num_lanes = num_lanes; in j721e_pcie_probe()
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| /linux/drivers/pci/controller/ |
| H A D | pcie-mediatek-gen3.c | 186 * @num_lanes: Number of PCIe lanes for this port
207 u8 num_lanes; member
420 if (pcie->num_lanes) { in mtk_pcie_startup_port()
424 if (pcie->num_lanes > 1) in mtk_pcie_startup_port()
426 GENMASK(fls(pcie->num_lanes >> 2), 0)); in mtk_pcie_startup_port()
860 u32 num_lanes; in mtk_pcie_parse_port() local
907 ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes); in mtk_pcie_parse_port()
909 if (num_lanes == 0 || num_lanes > 16 || in mtk_pcie_parse_port()
910 (num_lanes ! in mtk_pcie_parse_port()
[all...] |
| /linux/drivers/media/i2c/ |
| H A D | ov8858.c | 121 unsigned int num_lanes; member
1340 reg_list = ov8858->num_lanes == 4 in ov8858_start_stream()
1717 pixel_rate = OV8858_LINK_FREQ * 2 * ov8858->num_lanes / 10; in ov8858_init_ctrls()
1802 ov8858->global_regs = ov8858->num_lanes == 4 in ov8858_check_sensor_id()
1805 } else if (ov8858->num_lanes == 2) { in ov8858_check_sensor_id()
1855 ov8858->num_lanes = vep.bus.mipi_csi2.num_data_lanes; in ov8858_parse_of()
1856 switch (ov8858->num_lanes) { in ov8858_parse_of()
1862 ov8858->num_lanes); in ov8858_parse_of()
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| /linux/drivers/media/platform/samsung/exynos4-is/ |
| H A D | mipi-csis.c | 191 * @num_lanes: number of MIPI-CSI data lanes used
216 u32 num_lanes; member
322 mask = (1 << (state->num_lanes + 1)) - 1; in s5pcsis_system_enable()
360 val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (state->num_lanes - 1); in s5pcsis_set_params()
754 state->num_lanes = endpoint.bus.mipi_csi2.num_data_lanes; in s5pcsis_parse_dt()
792 if (state->num_lanes == 0 || state->num_lanes > state->max_num_lanes) { in s5pcsis_probe()
794 state->num_lanes, state->max_num_lanes); in s5pcsis_probe()
875 state->num_lanes, state->hs_settle, state->wclk_ext, in s5pcsis_probe()
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| /linux/drivers/media/platform/st/stm32/ |
| H A D | stm32-csi.c | 183 u8 num_lanes; member
362 for (i = 0; i < csidev->num_lanes; i++) { in stm32_csi_setup_lane_merger()
370 lmcfgr |= (csidev->num_lanes << STM32_CSI_LMCFGR_LANENB_SHIFT); in stm32_csi_setup_lane_merger()
470 fmt->bpp, 2 * csidev->num_lanes); in stm32_csi_start()
497 if (csidev->num_lanes == 2) { in stm32_csi_start()
943 csidev->num_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; in stm32_csi_parse_dt()
944 if (csidev->num_lanes > STM32_CSI_LANES_MAX) { in stm32_csi_parse_dt()
946 csidev->num_lanes); in stm32_csi_parse_dt()
1057 "Probed CSI with %u lanes\n", csidev->num_lanes); in stm32_csi_probe()
|
| /linux/drivers/staging/media/atomisp/pci/ |
| H A D | ia_css_input_port.h | 46 unsigned int num_lanes; /** Number of lanes used (4-lane port only) */ member
|
| /linux/drivers/phy/cadence/ |
| H A D | phy-cadence-torrent.c | 349 u32 num_lanes; member
1111 pll_bits = ((1 << inst->num_lanes) - 1); in cdns_torrent_dp_set_pll_en()
1130 u32 num_lanes, in cdns_torrent_dp_set_power_state() argument
1156 for (i = 0; i < num_lanes; i++) { in cdns_torrent_dp_set_power_state()
1177 struct cdns_torrent_inst *inst, u32 num_lanes) in cdns_torrent_dp_run() argument
1198 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes, in cdns_torrent_dp_run()
1203 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes, in cdns_torrent_dp_run()
1228 u32 rate, u32 num_lanes) in cdns_torrent_dp_pma_cmn_rate() argument
1269 for (i = 0; i < num_lanes; i++) in cdns_torrent_dp_pma_cmn_rate()
1400 if (dp->lanes > inst->num_lanes) in cdns_torrent_dp_verify_config()
1427 cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy * cdns_phy,struct cdns_torrent_inst * inst,u32 num_lanes) cdns_torrent_dp_set_a0_pll() argument
2482 int i, j, node, mlane, num_lanes, ret; cdns_torrent_phy_configure_multilink() local
[all...] |