| /linux/include/linux/soc/mediatek/ |
| H A D | mtk-cmdq.h | 26 struct cmdq_pkt;
104 int cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, size_t size);
111 void cmdq_pkt_destroy(struct cmdq_client *client, struct cmdq_pkt *pkt);
122 int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value);
134 int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
146 int cmdq_pkt_read_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, u16 addr_low,
163 int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
181 int cmdq_pkt_write_s_mask(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
194 int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx,
209 int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pk
[all...] |
| H A D | mtk-mmsys.h | 98 int height, struct cmdq_pkt *cmdq_pkt);
101 struct cmdq_pkt *cmdq_pkt);
104 u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt);
107 struct cmdq_pkt *cmdq_pkt);
110 struct cmdq_pkt *cmdq_pkt);
[all...] |
| /linux/drivers/gpu/drm/mediatek/ |
| H A D | mtk_mdp_rdma.c | 149 static void mtk_mdp_rdma_fifo_config(struct device *dev, struct cmdq_pkt *cmdq_pkt) in mtk_mdp_rdma_fifo_config() argument
153 mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | VAL_PRE_ULTRA_EN_ENABLE << 16 | in mtk_mdp_rdma_fifo_config()
161 void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt) in mtk_mdp_rdma_start() argument
165 mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg, in mtk_mdp_rdma_start()
169 void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt) in mtk_mdp_rdma_stop() argument
173 mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, in mtk_mdp_rdma_stop()
175 mtk_ddp_write(cmdq_pkt, in mtk_mdp_rdma_stop()
180 mtk_mdp_rdma_config(struct device * dev,struct mtk_mdp_rdma_cfg * cfg,struct cmdq_pkt * cmdq_pkt) mtk_mdp_rdma_config() argument
[all...] |
| H A D | mtk_ddp_comp.c | 69 void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, in mtk_ddp_write() argument
74 if (cmdq_pkt) in mtk_ddp_write()
75 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write()
82 void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, in mtk_ddp_write_relaxed() argument
87 if (cmdq_pkt) in mtk_ddp_write_relaxed()
88 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write_relaxed()
95 void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigne argument
130 mtk_dither_set_common(void __iomem * regs,struct cmdq_client_reg * cmdq_reg,unsigned int bpc,unsigned int cfg,unsigned int dither_en,struct cmdq_pkt * cmdq_pkt) mtk_dither_set_common() argument
156 mtk_dither_config(struct device * dev,unsigned int w,unsigned int h,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt) mtk_dither_config() argument
182 mtk_dither_set(struct device * dev,unsigned int bpc,unsigned int cfg,struct cmdq_pkt * cmdq_pkt) mtk_dither_set() argument
192 mtk_dsc_config(struct device * dev,unsigned int w,unsigned int h,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt) mtk_dsc_config() argument
222 mtk_od_config(struct device * dev,unsigned int w,unsigned int h,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt) mtk_od_config() argument
240 mtk_postmask_config(struct device * dev,unsigned int w,unsigned int h,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt) mtk_postmask_config() argument
[all...] |
| H A D | mtk_disp_ovl.c | 288 static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt, in mtk_ovl_set_afbc() argument
291 mtk_ddp_write_mask(cmdq_pkt, enabled ? OVL_LAYER_AFBC_EN(idx) : 0, in mtk_ovl_set_afbc()
297 struct cmdq_pkt *cmdq_pkt) in mtk_ovl_set_bit_depth() argument
308 mtk_ddp_write_mask(cmdq_pkt, OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx), in mtk_ovl_set_bit_depth()
315 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) in mtk_ovl_config() argument
320 mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_config()
327 mtk_ddp_write_relaxed(cmdq_pkt, OVL_COLOR_ALPH in mtk_ovl_config()
369 mtk_ovl_layer_on(struct device * dev,unsigned int idx,struct cmdq_pkt * cmdq_pkt) mtk_ovl_layer_on() argument
394 mtk_ovl_layer_off(struct device * dev,unsigned int idx,struct cmdq_pkt * cmdq_pkt) mtk_ovl_layer_off() argument
473 mtk_ovl_afbc_layer_config(struct mtk_disp_ovl * ovl,unsigned int idx,struct mtk_plane_pending_state * pending,struct cmdq_pkt * cmdq_pkt) mtk_ovl_afbc_layer_config() argument
495 mtk_ovl_layer_config(struct device * dev,unsigned int idx,struct mtk_plane_state * state,struct cmdq_pkt * cmdq_pkt) mtk_ovl_layer_config() argument
[all...] |
| H A D | mtk_disp_ccorr.c | 59 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) in mtk_ccorr_config() argument
63 mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, in mtk_ccorr_config()
65 mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, in mtk_ccorr_config()
112 struct cmdq_pkt *cmdq_pkt = NULL; in mtk_ccorr_ctm_set() local
124 mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], in mtk_ccorr_ctm_set()
126 mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], in mtk_ccorr_ctm_set()
128 mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], in mtk_ccorr_ctm_set()
130 mtk_ddp_write(cmdq_pkt, coeff in mtk_ccorr_ctm_set()
[all...] |
| H A D | mtk_ddp_comp.h | 50 struct cmdq_pkt;
58 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
74 struct cmdq_pkt *cmdq_pkt);
146 struct cmdq_pkt *cmdq_pkt) in mtk_ddp_comp_config() argument
149 comp->funcs->config(comp->dev, w, h, vrefresh, bpc, cmdq_pkt); in mtk_ddp_comp_config()
224 struct cmdq_pkt *cmdq_pkt) in mtk_ddp_comp_layer_config() argument
[all...] |
| H A D | mtk_disp_rdma.c | 186 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) in mtk_rdma_config() argument
193 mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_config()
195 mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_config()
213 mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON); in mtk_rdma_config()
260 struct cmdq_pkt *cmdq_pkt) in mtk_rdma_layer_config() argument
270 mtk_ddp_write_relaxed(cmdq_pkt, con, &rdma->cmdq_reg, rdma->regs, DISP_RDMA_MEM_CON); in mtk_rdma_layer_config()
273 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_layer_config()
276 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RG in mtk_rdma_layer_config()
[all...] |
| H A D | mtk_ethdr.h | 15 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
19 struct cmdq_pkt *cmdq_pkt);
|
| H A D | mtk_disp_ovl_adaptor.c | 134 struct cmdq_pkt *cmdq_pkt) in mtk_ovl_adaptor_layer_config() argument
161 mtk_merge_stop_cmdq(merge, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
162 mtk_mdp_rdma_stop(rdma_l, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
163 mtk_mdp_rdma_stop(rdma_r, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
164 mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
180 mtk_merge_advance_config(merge, l_w, r_w, pending->height, 0, 0, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
182 pending->height, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
190 mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
195 mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
211 mtk_ovl_adaptor_config(struct device * dev,unsigned int w,unsigned int h,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt) mtk_ovl_adaptor_config() argument
[all...] |
| H A D | mtk_disp_color.c | 62 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) in mtk_color_config() argument
66 mtk_ddp_write(cmdq_pkt, w, &color->cmdq_reg, color->regs, DISP_COLOR_WIDTH(color)); in mtk_color_config()
67 mtk_ddp_write(cmdq_pkt, h, &color->cmdq_reg, color->regs, DISP_COLOR_HEIGHT(color)); in mtk_color_config()
|
| H A D | mtk_crtc.c | 55 struct cmdq_pkt cmdq_handle;
479 struct cmdq_pkt *cmdq_handle) in mtk_crtc_ddp_config()
554 struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle; in mtk_crtc_update_config()
|
| /linux/drivers/soc/mediatek/ |
| H A D | mtk-mmsys.c | 164 struct cmdq_pkt *cmdq_pkt) in mtk_mmsys_update_bits() argument
169 if (mmsys->cmdq_base.size && cmdq_pkt) { in mtk_mmsys_update_bits()
170 ret = cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys, in mtk_mmsys_update_bits()
217 struct cmdq_pkt *cmdq_pkt) in mtk_mmsys_merge_async_config() argument
220 ~0, height << 16 | width, cmdq_pkt); in mtk_mmsys_merge_async_config()
225 struct cmdq_pkt *cmdq_pkt) in mtk_mmsys_hdr_config() argument
228 be_height << 16 | be_width, cmdq_pkt); in mtk_mmsys_hdr_config()
233 mtk_mmsys_mixer_in_config(struct device * dev,int idx,bool alpha_sel,u16 alpha,u8 mode,u32 biwidth,struct cmdq_pkt * cmdq_pkt) mtk_mmsys_mixer_in_config() argument
248 mtk_mmsys_mixer_in_channel_swap(struct device * dev,int idx,bool channel_swap,struct cmdq_pkt * cmdq_pkt) mtk_mmsys_mixer_in_channel_swap() argument
282 mtk_mmsys_vpp_rsz_merge_config(struct device * dev,u32 id,bool enable,struct cmdq_pkt * cmdq_pkt) mtk_mmsys_vpp_rsz_merge_config() argument
303 mtk_mmsys_vpp_rsz_dcm_config(struct device * dev,bool enable,struct cmdq_pkt * cmdq_pkt) mtk_mmsys_vpp_rsz_dcm_config() argument
[all...] |
| /linux/include/linux/mailbox/ |
| H A D | mtk-cmdq-mailbox.h | 70 struct cmdq_pkt *pkt;
73 struct cmdq_pkt { struct
74 va_basecmdq_pkt global() argument
75 pa_basecmdq_pkt global() argument
76 cmd_buf_sizecmdq_pkt global() argument
77 buf_sizecmdq_pkt global() argument
|
| /linux/drivers/media/platform/mediatek/mdp3/ |
| H A D | mtk-mdp3-cmdq.h | 27 struct cmdq_pkt pkt;
|
| /linux/drivers/mailbox/ |
| H A D | mtk-cmdq-mailbox.c | 73 struct cmdq_pkt *pkt; /* the packet sent from mailbox client */
377 struct cmdq_pkt *pkt = (struct cmdq_pkt *)data; in cmdq_mbox_send_data()
|