drm/mediatek/mtk_ddp_comp.c

69 void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
74 	if (cmdq_pkt)
75 		cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
82 void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
87 	if (cmdq_pkt)
88 		cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
95 void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
100 	if (cmdq_pkt) {
101 		cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,
130 			   unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
137 		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);
138 		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);
139 		mtk_ddp_write(cmdq_pkt,
144 		mtk_ddp_write(cmdq_pkt,
150 		mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
156 			      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
160 	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE);
161 	mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
164 			      DITHER_ENGINE_EN, cmdq_pkt);
182 			   unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
187 			      DISP_DITHERING, cmdq_pkt);
192 			   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
197 	mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
199 	mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
201 	mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
222 			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
226 	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
227 	mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
228 	mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
240 				unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
244 	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
246 	mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,