Searched refs:pre_pll_clk_div (Results 1 – 4 of 4) sorted by relevance
98 br->fr->pre_pll_clk_div); in print_pll() 173 rval = bounds_check(dev, pll_fr->pre_pll_clk_div, in check_fr_bounds() 175 lim_fr->max_pre_pll_clk_div, s, "pre_pll_clk_div"); in check_fr_bounds() 308 pll->ext_clk_freq_hz / pll_fr->pre_pll_clk_div; in __ccs_pll_calculate_vt_tree() 421 for (pll_fr->pre_pll_clk_div = min_pre_pll_clk_div; in ccs_pll_calculate_vt_tree() 422 pll_fr->pre_pll_clk_div <= max_pre_pll_clk_div; in ccs_pll_calculate_vt_tree() 423 pll_fr->pre_pll_clk_div += in ccs_pll_calculate_vt_tree() 425 2 - (pll_fr->pre_pll_clk_div & 1)) { in ccs_pll_calculate_vt_tree() 429 div = gcd(pre_mul * pll_fr->pre_pll_clk_div, pre_div); in ccs_pll_calculate_vt_tree() 430 mul = pre_mul * pll_fr->pre_pll_clk_div / di in ccs_pll_calculate_vt_tree() [all...]
62 * @pre_pll_clk_div: Pre-PLL clock divisor68 u16 pre_pll_clk_div; member
206 pre_pll_clk_div 0x0304 16
387 rval = ccs_write(sensor, PRE_PLL_CLK_DIV, pll->vt_fr.pre_pll_clk_div); in ccs_pll_configure() 428 pll->op_fr.pre_pll_clk_div); in ccs_pll_configure()