media/i2c/ccs-pll.c

98 				br->fr->pre_pll_clk_div);
173 	rval = bounds_check(dev, pll_fr->pre_pll_clk_div,
175 			    lim_fr->max_pre_pll_clk_div, s, "pre_pll_clk_div");
308 		pll->ext_clk_freq_hz / pll_fr->pre_pll_clk_div;
421 	for (pll_fr->pre_pll_clk_div = min_pre_pll_clk_div;
422 	     pll_fr->pre_pll_clk_div <= max_pre_pll_clk_div;
423 	     pll_fr->pre_pll_clk_div +=
425 		     2 - (pll_fr->pre_pll_clk_div & 1)) {
429 		div = gcd(pre_mul * pll_fr->pre_pll_clk_div, pre_div);
430 		mul = pre_mul * pll_fr->pre_pll_clk_div / div;
434 			pll_fr->pre_pll_clk_div, mul, div);
603  * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL
628 	 * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be
631 	dev_dbg(dev, "op_pre_pll_clk_div %u\n", op_pll_fr->pre_pll_clk_div);
643 			 op_pll_fr->pre_pll_clk_div * mul));
648 			   op_lim_bk->max_sys_clk_div * op_pll_fr->pre_pll_clk_div
660 				    op_pll_fr->pre_pll_clk_div * mul);
675 	more_mul_factor = lcm(div, op_pll_fr->pre_pll_clk_div) / div;
695 	op_pll_bk->sys_clk_div = div * i / op_pll_fr->pre_pll_clk_div;
699 		/ op_pll_fr->pre_pll_clk_div;
851 	for (op_pll_fr->pre_pll_clk_div = min_op_pre_pll_clk_div;
852 	     op_pll_fr->pre_pll_clk_div <= max_op_pre_pll_clk_div;
853 	     op_pll_fr->pre_pll_clk_div +=
855 		     2 - (op_pll_fr->pre_pll_clk_div & 1)) {