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Searched refs:clk_type (Results 1 – 25 of 46) sorted by relevance

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/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0_0_ppt.c631 enum smu_clk_type clk_type, in smu_v14_0_1_get_dpm_freq_by_index() argument
637 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v14_0_1_get_dpm_freq_by_index()
640 switch (clk_type) { in smu_v14_0_1_get_dpm_freq_by_index()
685 enum smu_clk_type clk_type, in smu_v14_0_0_get_dpm_freq_by_index() argument
691 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v14_0_0_get_dpm_freq_by_index()
694 switch (clk_type) { in smu_v14_0_0_get_dpm_freq_by_index()
729 enum smu_clk_type clk_type, in smu_v14_0_common_get_dpm_freq_by_index() argument
734 smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq); in smu_v14_0_common_get_dpm_freq_by_index()
735 else if (clk_type != SMU_VCLK1 && clk_type ! in smu_v14_0_common_get_dpm_freq_by_index()
742 smu_v14_0_0_clk_dpm_is_enabled(struct smu_context * smu,enum smu_clk_type clk_type) smu_v14_0_0_clk_dpm_is_enabled() argument
773 smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max) smu_v14_0_1_get_dpm_ultimate_freq() argument
895 smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max) smu_v14_0_0_get_dpm_ultimate_freq() argument
1009 smu_v14_0_common_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max) smu_v14_0_common_get_dpm_ultimate_freq() argument
1022 smu_v14_0_0_get_current_clk_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value) smu_v14_0_0_get_current_clk_freq() argument
1061 smu_v14_0_1_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * count) smu_v14_0_1_get_dpm_level_count() argument
1092 smu_v14_0_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * count) smu_v14_0_0_get_dpm_level_count() argument
1121 smu_v14_0_common_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * count) smu_v14_0_common_get_dpm_level_count() argument
1133 smu_v14_0_0_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf) smu_v14_0_0_print_clk_levels() argument
1209 smu_v14_0_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,u32 min,u32 max,bool __always_unused automatic) smu_v14_0_0_set_soft_freq_limited_range() argument
1265 smu_v14_0_0_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask) smu_v14_0_0_force_clk_levels() argument
1302 smu_v14_0_common_get_dpm_profile_freq(struct smu_context * smu,enum amd_dpm_forced_level level,enum smu_clk_type clk_type,uint32_t * min_clk,uint32_t * max_clk) smu_v14_0_common_get_dpm_profile_freq() argument
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H A Dsmu_v14_0.c1094 int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v14_0_get_dpm_ultimate_freq() argument
1101 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v14_0_get_dpm_ultimate_freq()
1102 switch (clk_type) { in smu_v14_0_get_dpm_ultimate_freq()
1130 clk_type); in smu_v14_0_get_dpm_ultimate_freq()
1163 enum smu_clk_type clk_type, in smu_v14_0_set_soft_freq_limited_range() argument
1171 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v14_0_set_soft_freq_limited_range()
1176 clk_type); in smu_v14_0_set_soft_freq_limited_range()
1207 enum smu_clk_type clk_type, in smu_v14_0_set_hard_freq_limited_range() argument
1217 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v14_0_set_hard_freq_limited_range()
1222 clk_type); in smu_v14_0_set_hard_freq_limited_range()
1441 smu_v14_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value) smu_v14_0_get_dpm_freq_by_index() argument
1475 smu_v14_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value) smu_v14_0_get_dpm_level_count() argument
1486 smu_v14_0_get_fine_grained_status(struct smu_context * smu,enum smu_clk_type clk_type,bool * is_fine_grained_dpm) smu_v14_0_get_fine_grained_status() argument
1524 smu_v14_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_14_0_dpm_table * single_dpm_table) smu_v14_0_set_single_dpm_table() argument
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddm_services_types.h82 #define DC_DECODE_PP_CLOCK_TYPE(clk_type) \ argument
83 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
84 (clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
85 (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : \
86 (clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \
87 (clk_type) == DM_PP_CLOCK_TYPE_DCEFCLK ? "DCEF" : \
88 (clk_type) == DM_PP_CLOCK_TYPE_SOCCLK ? "SoC" : \
89 (clk_type) == DM_PP_CLOCK_TYPE_PIXELCLK ? "Pixel" : \
90 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAYPHYCLK ? "Display PHY" : \
91 (clk_type)
254 enum dm_pp_clock_type clk_type; global() member
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H A Ddm_services.h184 * input: clk_type - display clk / sclk / mem clk
192 enum dm_pp_clock_type clk_type,
197 enum dm_pp_clock_type clk_type,
202 enum dm_pp_clock_type clk_type,
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_5_ppt.c595 enum smu_clk_type clk_type, in smu_v13_0_5_get_current_clk_freq() argument
600 switch (clk_type) { in smu_v13_0_5_get_current_clk_freq()
626 enum smu_clk_type clk_type, in smu_v13_0_5_get_dpm_level_count() argument
631 switch (clk_type) { in smu_v13_0_5_get_dpm_level_count()
655 enum smu_clk_type clk_type, in smu_v13_0_5_get_dpm_freq_by_index() argument
661 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_5_get_dpm_freq_by_index()
664 switch (clk_type) { in smu_v13_0_5_get_dpm_freq_by_index()
699 enum smu_clk_type clk_type) in smu_v13_0_5_clk_dpm_is_enabled() argument
703 switch (clk_type) { in smu_v13_0_5_clk_dpm_is_enabled()
728 enum smu_clk_type clk_type, in smu_v13_0_5_get_dpm_ultimate_freq() argument
816 smu_v13_0_5_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic) smu_v13_0_5_set_soft_freq_limited_range() argument
862 smu_v13_0_5_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf) smu_v13_0_5_print_clk_levels() argument
936 smu_v13_0_5_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask) smu_v13_0_5_force_clk_levels() argument
971 smu_v13_0_5_get_dpm_profile_freq(struct smu_context * smu,enum amd_dpm_forced_level level,enum smu_clk_type clk_type,uint32_t * min_clk,uint32_t * max_clk) smu_v13_0_5_get_dpm_profile_freq() argument
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H A Dyellow_carp_ppt.c726 enum smu_clk_type clk_type, in yellow_carp_get_current_clk_freq() argument
731 switch (clk_type) { in yellow_carp_get_current_clk_freq()
760 enum smu_clk_type clk_type, in yellow_carp_get_dpm_level_count() argument
765 switch (clk_type) { in yellow_carp_get_dpm_level_count()
789 enum smu_clk_type clk_type, in yellow_carp_get_dpm_freq_by_index() argument
795 if (!clk_table || clk_type >= SMU_CLK_COUNT) in yellow_carp_get_dpm_freq_by_index()
798 switch (clk_type) { in yellow_carp_get_dpm_freq_by_index()
833 enum smu_clk_type clk_type) in yellow_carp_clk_dpm_is_enabled() argument
837 switch (clk_type) { in yellow_carp_clk_dpm_is_enabled()
862 enum smu_clk_type clk_type, in yellow_carp_get_dpm_ultimate_freq() argument
950 yellow_carp_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic) yellow_carp_set_soft_freq_limited_range() argument
1006 yellow_carp_get_umd_pstate_clk_default(struct smu_context * smu,enum smu_clk_type clk_type) yellow_carp_get_umd_pstate_clk_default() argument
1042 yellow_carp_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf) yellow_carp_print_clk_levels() argument
1118 yellow_carp_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask) yellow_carp_force_clk_levels() argument
1155 yellow_carp_get_dpm_profile_freq(struct smu_context * smu,enum amd_dpm_forced_level level,enum smu_clk_type clk_type,uint32_t * min_clk,uint32_t * max_clk) yellow_carp_get_dpm_profile_freq() argument
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H A Dsmu_v13_0.c1483 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v13_0_get_dpm_ultimate_freq() argument
1490 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v13_0_get_dpm_ultimate_freq()
1491 ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit); in smu_v13_0_get_dpm_ultimate_freq()
1506 clk_type); in smu_v13_0_get_dpm_ultimate_freq()
1539 enum smu_clk_type clk_type, in smu_v13_0_set_soft_freq_limited_range() argument
1547 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v13_0_set_soft_freq_limited_range()
1552 clk_type); in smu_v13_0_set_soft_freq_limited_range()
1791 enum smu_clk_type clk_type, in smu_v13_0_get_boot_freq_by_index() argument
1796 switch (clk_type) { in smu_v13_0_get_boot_freq_by_index()
1825 enum smu_clk_type clk_type, uint16_ in smu_v13_0_get_dpm_freq_by_index() argument
1858 smu_v13_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value) smu_v13_0_get_dpm_level_count() argument
1872 smu_v13_0_get_fine_grained_status(struct smu_context * smu,enum smu_clk_type clk_type,bool * is_fine_grained_dpm) smu_v13_0_get_fine_grained_status() argument
1910 smu_v13_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_13_0_dpm_table * single_dpm_table) smu_v13_0_set_single_dpm_table() argument
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/linux/drivers/media/platform/qcom/iris/
H A Diris_resources.c89 static struct clk *iris_get_clk_by_type(struct iris_core *core, enum platform_clk_type clk_type) in iris_get_clk_by_type() argument
98 if (clk_tbl[i].clk_type == clk_type) { in iris_get_clk_by_type()
109 int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type) in iris_prepare_enable_clock() argument
113 clock = iris_get_clk_by_type(core, clk_type); in iris_prepare_enable_clock()
120 int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type) in iris_disable_unprepare_clock() argument
124 clock = iris_get_clk_by_type(core, clk_type); in iris_disable_unprepare_clock()
H A Diris_resources.h15 int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type);
16 int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type);
/linux/drivers/clk/imx/
H A Dclk-scu.h34 int num_parents, u32 rsrc_id, u8 clk_type);
38 u32 rsrc_id, u8 clk_type);
52 u8 clk_type) in imx_clk_scu() argument
54 return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type); in imx_clk_scu()
58 int num_parents, u32 rsrc_id, u8 clk_type) in imx_clk_scu2() argument
60 return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type); in imx_clk_scu2()
H A Dclk-scu.c33 u8 clk_type; member
47 * @clk_type: type of this clock resource
52 u8 clk_type; member
243 msg.data.req.clk = clk->clk_type; in clk_scu_recalc_rate()
316 msg.clk = clk->clk_type; in clk_scu_set_rate()
334 msg.data.req.clk = clk->clk_type; in clk_scu_get_parent()
361 msg.clk = clk->clk_type; in clk_scu_set_parent()
406 clk->clk_type, true, false); in clk_scu_prepare()
421 clk->clk_type, false, false); in clk_scu_unprepare()
453 u32 rsrc_id, u8 clk_type) in __imx_clk_scu() argument
670 imx_clk_scu_alloc_dev(const char * name,const char * const * parents,int num_parents,u32 rsrc_id,u8 clk_type) imx_clk_scu_alloc_dev() argument
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c202 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, in renoir_get_dpm_clk_limited() argument
207 if (!clk_table || clk_type >= SMU_CLK_COUNT) in renoir_get_dpm_clk_limited()
210 switch (clk_type) { in renoir_get_dpm_clk_limited()
281 enum smu_clk_type clk_type, in renoir_get_dpm_ultimate_freq() argument
289 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in renoir_get_dpm_ultimate_freq()
290 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
325 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
337 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); in renoir_get_dpm_ultimate_freq()
342 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max); in renoir_get_dpm_ultimate_freq()
353 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
495 renoir_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf) renoir_print_clk_levels() argument
692 enum smu_clk_type clk_type; renoir_force_dpm_limit_value() local
719 enum smu_clk_type clk_type; renoir_unforce_dpm_levels() local
722 enum smu_clk_type clk_type; renoir_unforce_dpm_levels() member
793 renoir_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask) renoir_force_clk_levels() argument
911 renior_set_dpm_profile_freq(struct smu_context * smu,enum amd_dpm_forced_level level,enum smu_clk_type clk_type) renior_set_dpm_profile_freq() argument
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/linux/drivers/gpu/drm/amd/pm/swsmu/
H A Damdgpu_smu.c63 enum smu_clk_type clk_type,
145 enum smu_clk_type clk_type; in smu_set_soft_freq_range() local
148 clk_type = smu_convert_to_smuclk(type); in smu_set_soft_freq_range()
149 if (clk_type == SMU_CLK_COUNT) in smu_set_soft_freq_range()
154 clk_type, in smu_set_soft_freq_range()
163 enum smu_clk_type clk_type, in smu_get_dpm_freq_range() argument
174 clk_type, in smu_get_dpm_freq_range()
520 enum smu_clk_type clk_type; in smu_restore_dpm_user_profile() local
522 for (clk_type = 0; clk_type < SMU_CLK_COUN in smu_restore_dpm_user_profile()
2568 smu_force_smuclk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask) smu_force_smuclk_levels() argument
2598 enum smu_clk_type clk_type; smu_force_ppclk_levels() local
2967 smu_print_smuclk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf) smu_print_smuclk_levels() argument
2982 enum smu_clk_type clk_type; smu_convert_to_smuclk() local
3049 enum smu_clk_type clk_type; smu_print_ppclk_levels() local
3061 enum smu_clk_type clk_type; smu_emit_ppclk_levels() local
3377 enum smu_clk_type clk_type; smu_get_clock_by_type_with_latency() local
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dvangogh_ppt.c519 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, in vangogh_get_dpm_clk_limited() argument
524 if (!clk_table || clk_type >= SMU_CLK_COUNT) in vangogh_get_dpm_clk_limited()
527 switch (clk_type) { in vangogh_get_dpm_clk_limited()
563 enum smu_clk_type clk_type, char *buf) in vangogh_print_legacy_clk_levels() argument
580 switch (clk_type) { in vangogh_print_legacy_clk_levels()
635 switch (clk_type) { in vangogh_print_legacy_clk_levels()
642 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; in vangogh_print_legacy_clk_levels()
643 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value); in vangogh_print_legacy_clk_levels()
665 enum smu_clk_type clk_type, cha in vangogh_print_clk_levels() argument
786 vangogh_common_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf) vangogh_common_print_clk_levels() argument
853 vangogh_clk_dpm_is_enabled(struct smu_context * smu,enum smu_clk_type clk_type) vangogh_clk_dpm_is_enabled() argument
885 vangogh_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max) vangogh_get_dpm_ultimate_freq() argument
1076 vangogh_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic) vangogh_set_soft_freq_limited_range() argument
1159 vangogh_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask) vangogh_force_clk_levels() argument
1269 enum smu_clk_type clk_type; vangogh_force_dpm_limit_value() local
1297 enum smu_clk_type clk_type; vangogh_unforce_dpm_levels() local
1300 enum smu_clk_type clk_type; vangogh_unforce_dpm_levels() member
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H A Dcyan_skillfish_ppt.c260 enum smu_clk_type clk_type, in cyan_skillfish_get_current_clk_freq() argument
265 switch (clk_type) { in cyan_skillfish_get_current_clk_freq()
291 enum smu_clk_type clk_type, in cyan_skillfish_print_clk_levels() argument
300 switch (clk_type) { in cyan_skillfish_print_clk_levels()
327 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value); in cyan_skillfish_print_clk_levels()
334 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value); in cyan_skillfish_print_clk_levels()
536 enum smu_clk_type clk_type, in cyan_skillfish_get_dpm_ultimate_freq() argument
543 switch (clk_type) { in cyan_skillfish_get_dpm_ultimate_freq()
550 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &low); in cyan_skillfish_get_dpm_ultimate_freq()
H A Dsmu_v11_0.c1057 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu_v11_0_display_clock_voltage_request() local
1064 switch (clk_type) { in smu_v11_0_display_clock_voltage_request()
1710 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v11_0_get_dpm_ultimate_freq() argument
1717 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v11_0_get_dpm_ultimate_freq()
1718 switch (clk_type) { in smu_v11_0_get_dpm_ultimate_freq()
1746 clk_type); in smu_v11_0_get_dpm_ultimate_freq()
1770 enum smu_clk_type clk_type, in smu_v11_0_set_soft_freq_limited_range() argument
1778 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v11_0_set_soft_freq_limited_range()
1783 clk_type); in smu_v11_0_set_soft_freq_limited_range()
1814 enum smu_clk_type clk_type, in smu_v11_0_set_hard_freq_limited_range() argument
1977 smu_v11_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value) smu_v11_0_get_dpm_freq_by_index() argument
2015 smu_v11_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value) smu_v11_0_get_dpm_level_count() argument
2025 smu_v11_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_11_0_dpm_table * single_dpm_table) smu_v11_0_set_single_dpm_table() argument
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H A Dnavi10_ppt.c1184 enum smu_clk_type clk_type, in navi10_get_current_clk_freq_by_table() argument
1192 clk_type); in navi10_get_current_clk_freq_by_table()
1224 static int navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) in navi10_is_support_fine_grained_dpm() argument
1232 clk_type); in navi10_is_support_fine_grained_dpm()
1258 enum smu_clk_type clk_type, in navi10_emit_clk_levels() argument
1277 switch (clk_type) { in navi10_emit_clk_levels()
1287 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); in navi10_emit_clk_levels()
1291 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); in navi10_emit_clk_levels()
1295 ret = navi10_is_support_fine_grained_dpm(smu, clk_type); in navi10_emit_clk_levels()
1302 clk_type, in navi10_emit_clk_levels()
1469 navi10_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf) navi10_print_clk_levels() argument
1660 navi10_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask) navi10_force_clk_levels() argument
1801 navi10_get_clock_by_type_with_latency(struct smu_context * smu,enum smu_clk_type clk_type,struct pp_clock_levels_with_latency * clocks) navi10_get_clock_by_type_with_latency() argument
[all...]
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c111 enum dm_pp_clock_type clk_type, in get_default_clock_levels() argument
120 switch (clk_type) { in get_default_clock_levels()
294 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type() argument
303 dc_to_pp_clock_type(clk_type), &pp_clks)) { in dm_pp_get_clock_levels_by_type()
305 get_default_clock_levels(clk_type, dc_clks); in dm_pp_get_clock_levels_by_type()
309 pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type); in dm_pp_get_clock_levels_by_type()
332 if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) { in dm_pp_get_clock_levels_by_type()
345 } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) { in dm_pp_get_clock_levels_by_type()
361 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type_with_latency() argument
369 dc_to_pp_clock_type(clk_type), in dm_pp_get_clock_levels_by_type_with_latency()
381 dm_pp_get_clock_levels_by_type_with_voltage(const struct dc_context * ctx,enum dm_pp_clock_type clk_type,struct dm_pp_clock_levels_with_voltage * clk_level_info) dm_pp_get_clock_levels_by_type_with_voltage() argument
[all...]
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Dsmu_v13_0.h215 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
218 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
228 enum smu_clk_type clk_type,
232 enum smu_clk_type clk_type, uint16_t level,
296 enum smu_clk_type clk_type,
H A Dsmu_v14_0.h185 int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
188 int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
192 enum smu_clk_type clk_type,
203 enum smu_clk_type clk_type,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
H A Ddcn401_clk_mgr.h115 unsigned int dcn401_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);
/linux/drivers/input/
H A Devdev.c49 enum input_clock_type clk_type; member
146 struct timespec64 ts = ktime_to_timespec64(ev_time[client->clk_type]); in __evdev_queue_syn_dropped()
177 enum input_clock_type clk_type; in evdev_set_clk_type() local
182 clk_type = INPUT_CLK_REAL; in evdev_set_clk_type()
185 clk_type = INPUT_CLK_MONO; in evdev_set_clk_type()
188 clk_type = INPUT_CLK_BOOT; in evdev_set_clk_type()
194 if (client->clk_type != clk_type) { in evdev_set_clk_type()
195 client->clk_type = clk_type; in evdev_set_clk_type()
[all...]
/linux/drivers/phy/
H A Dphy-xgene.c535 enum clk_type_t clk_type; /* Input clock selection */ member
706 enum clk_type_t clk_type) in xgene_phy_cfg_cmu_clk_type() argument
719 if (clk_type == CLK_EXT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
729 } else if (clk_type == CLK_INT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
739 } else if (clk_type == CLK_INT_SING) { in xgene_phy_cfg_cmu_clk_type()
760 enum clk_type_t clk_type) in xgene_phy_sata_cfg_cmu_core() argument
806 if (clk_type == CLK_EXT_DIFF) in xgene_phy_sata_cfg_cmu_core()
1137 enum clk_type_t clk_type) in xgene_phy_cal_rdy_chk() argument
1237 enum clk_type_t clk_type) in xgene_phy_pdwn_force_vco() argument
1254 enum clk_type_t clk_type, in in xgene_phy_hw_init_sata() argument
1318 xgene_phy_hw_initialize(struct xgene_phy_ctx * ctx,enum clk_type_t clk_type,int ssc_enable) xgene_phy_hw_initialize() argument
[all...]
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h103 enum clk_type { enum
342 unsigned int (*get_max_clock_khz)(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);
/linux/drivers/nfc/s3fwrn5/
H A Dnci.h44 __u8 clk_type; member

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