1*bb8a95aaSDikshita Agarwal /* SPDX-License-Identifier: GPL-2.0-only */ 2*bb8a95aaSDikshita Agarwal /* 3*bb8a95aaSDikshita Agarwal * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4*bb8a95aaSDikshita Agarwal */ 5*bb8a95aaSDikshita Agarwal 6*bb8a95aaSDikshita Agarwal #ifndef __IRIS_RESOURCES_H__ 7*bb8a95aaSDikshita Agarwal #define __IRIS_RESOURCES_H__ 8*bb8a95aaSDikshita Agarwal 9*bb8a95aaSDikshita Agarwal struct iris_core; 10*bb8a95aaSDikshita Agarwal 11*bb8a95aaSDikshita Agarwal int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev); 12*bb8a95aaSDikshita Agarwal int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev); 13*bb8a95aaSDikshita Agarwal int iris_unset_icc_bw(struct iris_core *core); 14*bb8a95aaSDikshita Agarwal int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw); 15*bb8a95aaSDikshita Agarwal int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type); 16*bb8a95aaSDikshita Agarwal int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type); 17*bb8a95aaSDikshita Agarwal 18*bb8a95aaSDikshita Agarwal #endif 19