| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.h | 174 SRII(PIXEL_RATE_CNTL, OTG, 0), \
175 SRII(PIXEL_RATE_CNTL, OTG, 1),\
176 SRII(PIXEL_RATE_CNTL, OTG, 2),\
177 SRII(PIXEL_RATE_CNTL, OTG, 3),\
178 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
179 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
180 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
181 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
219 SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst),\
220 SRI_ARR(OTG_VUPDATE_PARAM, OTG, ins
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn314/ |
| H A D | dcn314_optc.h | 33 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
34 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
35 SRI(OTG_VREADY_PARAM, OTG, inst),\
36 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
37 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
38 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
39 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
40 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
41 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
42 SRI(OTG_H_TOTAL, OTG, ins
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn31/ |
| H A D | dcn31_optc.h | 32 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
33 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
34 SRI(OTG_VREADY_PARAM, OTG, inst),\
35 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
36 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
37 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
38 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
39 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
40 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
41 SRI(OTG_H_TOTAL, OTG, ins
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn30/ |
| H A D | dcn30_optc.h | 34 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
35 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
36 SRI(OTG_VREADY_PARAM, OTG, inst),\
37 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
38 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
39 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
40 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
41 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
42 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
43 SRI(OTG_H_TOTAL, OTG, ins
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_clock_source.h | 72 SRII(PIXEL_RATE_CNTL, OTG, 0),\
73 SRII(PIXEL_RATE_CNTL, OTG, 1),\
74 SRII(PIXEL_RATE_CNTL, OTG, 2),\
75 SRII(PIXEL_RATE_CNTL, OTG, 3),\
76 SRII(PIXEL_RATE_CNTL, OTG, 4),\
77 SRII(PIXEL_RATE_CNTL, OTG, 5)
85 SRII(PIXEL_RATE_CNTL, OTG, 0),\
86 SRII(PIXEL_RATE_CNTL, OTG, 1)
98 SRII(PIXEL_RATE_CNTL, OTG, 0),\
99 SRII(PIXEL_RATE_CNTL, OTG,
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| H A D | dcn31_dccg.h | 47 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
48 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
49 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
50 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
113 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
114 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
115 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
116 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
117 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
118 DCCG_SFII(OTG, PIXEL_RATE_CNT
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/ |
| H A D | dcn10_optc.h | 35 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
36 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
37 SRI(OTG_VREADY_PARAM, OTG, inst),\
38 SRI(OTG_BLANK_CONTROL, OTG, inst),\
39 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
40 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
41 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
42 SRI(OTG_H_TOTAL, OTG, inst),\
43 SRI(OTG_H_BLANK_START_END, OTG, inst),\
44 SRI(OTG_H_SYNC_A, OTG, ins
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn32/ |
| H A D | dcn32_dccg.h | 80 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
81 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
82 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
83 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
84 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
85 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\
86 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\
87 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\
88 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
89 DCCG_SFII(OTG, PIXEL_RATE_CNT
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| H A D | dcn20_dccg.h | 38 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
39 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
46 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
47 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
48 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
49 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5)
81 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
82 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXE
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn303/ |
| H A D | dcn303_dccg.h | 38 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
39 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1)
59 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
60 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
61 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
62 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXE
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| H A D | dcn314_dccg.h | 52 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
53 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
54 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
55 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
111 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
112 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
113 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
114 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
115 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
116 DCCG_SFII(OTG, PIXEL_RATE_CNT
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| H A D | dcn35_dccg.h | 102 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
103 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
104 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
105 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
106 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
107 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\
108 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\
109 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\
110 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
111 DCCG_SFII(OTG, PIXEL_RATE_CNT
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.h | 478 SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \
479 SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \
480 SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \
481 SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \
482 SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \
483 SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
484 SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \
485 SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \
486 SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \
487 SRI_ARR(OTG_H_TOTAL, OTG, ins
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.h | 35 SRII(PIXEL_RATE_CNTL, OTG, 0), \
36 SRII(PIXEL_RATE_CNTL, OTG, 1),\
37 SRII(PIXEL_RATE_CNTL, OTG, 2),\
38 SRII(PIXEL_RATE_CNTL, OTG, 3),\
39 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
40 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
41 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
42 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
|
| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/ |
| H A D | dcn20_optc.h | 33 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
34 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
35 SRI(OTG_GSL_WINDOW_X, OTG, inst),\
36 SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
37 SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
38 SRI(OTG_DSC_START_POSITION, OTG, inst),\
39 SRI(OTG_CRC_CNTL2, OTG, inst),\
45 SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \
46 SRI(OTG_DRR_CONTROL, OTG, inst),\
47 SRI(OTG_PIPE_UPDATE_STATUS, OTG, ins
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/ |
| H A D | dcn401_dccg.h | 77 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
78 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
79 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
80 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
81 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
82 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
83 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXE
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/ |
| H A D | dcn201_optc.h | 33 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
34 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
35 SRI(OTG_GSL_WINDOW_X, OTG, inst),\
36 SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
37 SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
38 SRI(OTG_DSC_START_POSITION, OTG, inst),\
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.h | 208 SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 0, index), \
209 SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 1, index), \
210 SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 2, index), \
211 SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 3, index)
1000 SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \
1001 SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \
1002 SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \
1003 SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \
1004 SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \
1005 SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, ins
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn30/ |
| H A D | dcn30_dccg.h | 35 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
36 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
37 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
38 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce/ |
| H A D | dce_hwseq.h | 224 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
225 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
226 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
227 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
258 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
259 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
260 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
261 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
262 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \
263 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG,
[all...] |
| /linux/drivers/usb/phy/ |
| H A D | Kconfig | 19 Enable this to support the USB OTG transceiver in AB8500 chip.
24 tristate "Freescale USB OTG Transceiver Driver"
29 Enable this to support Freescale USB OTG transceiver.
68 Enable this to support the USB OTG transceiver on TWL6030
70 and OTG SRP events capabilities. For all other transceiver functionality
86 NOT support role switch. OTG devices that can do role switch
91 tristate "OMAP USB OTG controller driver"
94 Enable this to support some transceivers on OMAP1 platforms. OTG
124 and OTG drivers (to be selected separately).
154 Enable this to support ULPI connected USB OTG transceiver
[all...] |
| /linux/Documentation/devicetree/bindings/extcon/ |
| H A D | extcon-max3355.txt | 1 Maxim Integrated MAX3355 USB OTG chip
5 integrated USB OTG dual-role transceiver to function as a USB OTG dual-role
|
| /linux/Documentation/ABI/stable/ |
| H A D | sysfs-class-udc | 6 Indicates if an OTG A-Host supports HNP at an alternate port.
14 Indicates if an OTG A-Host supports HNP at this port.
22 Indicates if an OTG A-Host enabled HNP support.
38 Indicates that this port is the default Host on an OTG session
47 Indicates that this port support OTG.
|
| /linux/drivers/usb/core/ |
| H A D | Kconfig | 43 no more than 30 seconds (as required by the USB OTG spec).
60 bool "OTG support"
63 The most notable feature of USB OTG is support for a
73 bool "Rely on OTG and EH Targeted Peripherals List"
79 USB OTG and EH specification for all devices not on your product's
88 external hubs. OTG hosts are allowed to reduce hardware
90 are "Embedded Hosts" that don't offer OTG support.
93 tristate "USB 2.0 OTG FSM implementation"
97 Implements OTG Finite State Machine as specified in On-The-Go
|
| /linux/Documentation/driver-api/usb/ |
| H A D | gadget.rst | 28 - USB "On-The-Go" (OTG) support, in conjunction with updates to the
32 API. This helps the OTG support, and looks forward to more-symmetric
151 OTG-capable systems will also need to include a standard Linux-USB host
153 (HCDs), *USB Device Drivers* to support the OTG "Targeted Peripheral
154 List", and so forth. There will also be an *OTG Controller Driver*,
157 new OTG protocols (HNP and SRP). Roles switch (host to peripheral, or
262 configurations, unless the hardware prevents such operation. For OTG
263 devices, each configuration descriptor includes an OTG descriptor.
271 allowed by that configuration. For OTG devices, setting a
296 Note that the lifecycle above can be slightly different for OTG device
[all...] |