| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 292 static void calculate_wm_set_for_vlevel(int vlevel, in calculate_wm_set_for_vlevel() argument
301 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
303 pipes[0].clks_cfg.voltage = vlevel; in calculate_wm_set_for_vlevel()
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
305 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
433 int vlevel, vlevel_max; in dcn301_fpu_calculate_wm_and_dlg() local
445 vlevel = 0; in dcn301_fpu_calculate_wm_and_dlg()
447 vlevel = vlevel_max; in dcn301_fpu_calculate_wm_and_dlg()
448 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, in dcn301_fpu_calculate_wm_and_dlg()
452 vlevel = clamp(vlevel_req, 2, vlevel_max); in dcn301_fpu_calculate_wm_and_dlg()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 279 int vlevel) in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() argument
284 …enum clock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context-… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
290 …vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_suppor… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
293 …dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, DC_VALIDATE_MODE_AND_PROGRAMMIN… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
296 if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
298 …vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_suppor… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
300 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
301 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported) in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
478 unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel; in dcn32_set_phantom_stream_timing() local
479 …unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcCo… in dcn32_set_phantom_stream_timing()
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| H A D | dcn32_fpu.h | 57 int vlevel);
65 int vlevel);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 1144 int vlevel) in dcn20_calculate_dlg_params() argument
1164 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] in dcn20_calculate_dlg_params()
1218 …context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel]… in dcn20_calculate_dlg_params()
1219 …context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel… in dcn20_calculate_dlg_params()
1225 …bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] … in dcn20_calculate_dlg_params()
1734 int vlevel, in dcn20_calculate_wm() argument
1746 …pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw… in dcn20_calculate_wm()
1750 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; in dcn20_calculate_wm()
1759 …context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from… in dcn20_calculate_wm()
1790 pipes[0].clks_cfg.voltage = vlevel; in dcn20_calculate_wm()
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| H A D | dcn20_fpu.h | 43 int vlevel);
53 int vlevel,
70 int vlevel,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 307 int vlevel) in dcn30_fpu_calculate_wm_and_dlg() argument
311 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
312 …bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clo… in dcn30_fpu_calculate_wm_and_dlg()
334 context, pipes, pipe_cnt, vlevel); in dcn30_fpu_calculate_wm_and_dlg()
342 dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, in dcn30_fpu_calculate_wm_and_dlg()
345 dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
346 …pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_ch… in dcn30_fpu_calculate_wm_and_dlg()
353 pipes[0].clks_cfg.voltage = vlevel; in dcn30_fpu_calculate_wm_and_dlg()
355 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
362 if (vlevel == 0) { in dcn30_fpu_calculate_wm_and_dlg()
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| H A D | dcn30_fpu.h | 47 int vlevel);
67 int vlevel);
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| /linux/drivers/soc/qcom/ |
| H A D | spm.c | 333 unsigned int vlevel, volt_sel; in smp_set_vdd_v1_1() local
337 vlevel = volt_sel | 0x80; /* band */ in smp_set_vdd_v1_1()
355 vctl = FIELD_SET(vctl, SPM_VCTL_VLVL, vlevel); in smp_set_vdd_v1_1()
356 data0 = FIELD_SET(data0, SPM_PMIC_DATA_0_VLVL, vlevel); in smp_set_vdd_v1_1()
365 sts, sts == vlevel, in smp_set_vdd_v1_1()
368 dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel); in smp_set_vdd_v1_1()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.h | 73 int vlevel);
106 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
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| H A D | dcn30_resource.c | 1671 int pipe_cnt, i, pipe_idx, vlevel = 0; in dcn30_internal_validate_bw() local
1699 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1701 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1702 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn30_internal_validate_bw()
1705 …(validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING || vlevel == context->bw_ctx.dml.soc.num_states… in dcn30_internal_validate_bw()
1706 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported)) { in dcn30_internal_validate_bw()
1718 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1719 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1722 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn30_internal_validate_bw()
1729 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1854 int vlevel, in dcn20_validate_apply_pipe_split_flags() argument
1917 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1918 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 && in dcn20_validate_apply_pipe_split_flags()
1919 v->ModeSupport[vlevel][0]) in dcn20_validate_apply_pipe_split_flags()
1922 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
1923 vlevel = vlevel_split; in dcn20_validate_apply_pipe_split_flags()
1941 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4) in dcn20_validate_apply_pipe_split_flags()
1943 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2) in dcn20_validate_apply_pipe_split_flags()
1957 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1; in dcn20_validate_apply_pipe_split_flags()
1961 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1; in dcn20_validate_apply_pipe_split_flags()
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| H A D | dcn20_resource.h | 129 int vlevel,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 486 int vlevel) in dcn31_calculate_wm_and_dlg_fp() argument
489 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
506 pipes[0].clks_cfg.voltage = vlevel; in dcn31_calculate_wm_and_dlg_fp()
508 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
559 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); in dcn31_calculate_wm_and_dlg_fp()
562 …context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_d… in dcn31_calculate_wm_and_dlg_fp()
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| H A D | dcn31_fpu.h | 45 int vlevel);
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 806 int pipe_cnt, i, pipe_idx, vlevel; in dcn21_fast_validate_bw() local
829 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
831 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
841 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
842 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
846 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn21_fast_validate_bw()
905 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn21_fast_validate_bw()
936 *vlevel_out = vlevel; in dcn21_fast_validate_bw()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.h | 47 int vlevel);
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| H A D | dcn31_resource.c | 1764 int vlevel) in dcn31_calculate_wm_and_dlg() argument
1767 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); in dcn31_calculate_wm_and_dlg()
1800 int vlevel = 0; in dcn31_validate_bandwidth() local
1812 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, true); in dcn31_validate_bandwidth()
1829 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn31_validate_bandwidth()
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| /linux/arch/arm64/kvm/ |
| H A D | arch_timer.c | 895 bool vlevel, plevel; in kvm_timer_should_notify_user() local
900 vlevel = sregs->device_irq_level & KVM_ARM_DEV_EL1_VTIMER; in kvm_timer_should_notify_user()
903 return kvm_timer_should_fire(vtimer) != vlevel || in kvm_timer_should_notify_user()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 704 bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel) in dcn32_subvp_vblank_admissable() argument
744 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) in dcn32_subvp_vblank_admissable()
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| H A D | dcn32_resource.c | 1786 int vlevel = 0; in dml1_validate() local
1805 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode); in dml1_validate()
1821 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dml1_validate()
2093 int vlevel) in dcn32_calculate_wm_and_dlg() argument
2096 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); in dcn32_calculate_wm_and_dlg()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 93 int vlevel);
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 1738 int vlevel = 0; in dcn314_validate_bandwidth() local
1751 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, false); in dcn314_validate_bandwidth()
1768 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn314_validate_bandwidth()
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