1c8b3538dSRodrigo Siqueira /* SPDX-License-Identifier: MIT */ 2c8b3538dSRodrigo Siqueira /* 3c8b3538dSRodrigo Siqueira * Copyright 2021 Advanced Micro Devices, Inc. 4c8b3538dSRodrigo Siqueira * 5c8b3538dSRodrigo Siqueira * Permission is hereby granted, free of charge, to any person obtaining a 6c8b3538dSRodrigo Siqueira * copy of this software and associated documentation files (the "Software"), 7c8b3538dSRodrigo Siqueira * to deal in the Software without restriction, including without limitation 8c8b3538dSRodrigo Siqueira * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9c8b3538dSRodrigo Siqueira * and/or sell copies of the Software, and to permit persons to whom the 10c8b3538dSRodrigo Siqueira * Software is furnished to do so, subject to the following conditions: 11c8b3538dSRodrigo Siqueira * 12c8b3538dSRodrigo Siqueira * The above copyright notice and this permission notice shall be included in 13c8b3538dSRodrigo Siqueira * all copies or substantial portions of the Software. 14c8b3538dSRodrigo Siqueira * 15c8b3538dSRodrigo Siqueira * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16c8b3538dSRodrigo Siqueira * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17c8b3538dSRodrigo Siqueira * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18c8b3538dSRodrigo Siqueira * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19c8b3538dSRodrigo Siqueira * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20c8b3538dSRodrigo Siqueira * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21c8b3538dSRodrigo Siqueira * OTHER DEALINGS IN THE SOFTWARE. 22c8b3538dSRodrigo Siqueira * 23c8b3538dSRodrigo Siqueira * Authors: AMD 24c8b3538dSRodrigo Siqueira * 25c8b3538dSRodrigo Siqueira */ 26cf689e86SMelissa Wen #include "core_types.h" 27c8b3538dSRodrigo Siqueira 28ee373411SQingqing Zhuo #ifndef __DCN20_FPU_H__ 29ee373411SQingqing Zhuo #define __DCN20_FPU_H__ 30c8b3538dSRodrigo Siqueira 31c8b3538dSRodrigo Siqueira void dcn20_populate_dml_writeback_from_context(struct dc *dc, 32c8b3538dSRodrigo Siqueira struct resource_context *res_ctx, 33c8b3538dSRodrigo Siqueira display_e2e_pipe_params_st *pipes); 34c8b3538dSRodrigo Siqueira 35cf689e86SMelissa Wen void dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params, 36cf689e86SMelissa Wen struct dc_state *context, 37cf689e86SMelissa Wen display_e2e_pipe_params_st *pipes, 38cf689e86SMelissa Wen int pipe_cnt, int i); 39cf689e86SMelissa Wen void dcn20_calculate_dlg_params(struct dc *dc, 40cf689e86SMelissa Wen struct dc_state *context, 41cf689e86SMelissa Wen display_e2e_pipe_params_st *pipes, 42cf689e86SMelissa Wen int pipe_cnt, 43cf689e86SMelissa Wen int vlevel); 44cf689e86SMelissa Wen int dcn20_populate_dml_pipes_from_context(struct dc *dc, 45cf689e86SMelissa Wen struct dc_state *context, 46cf689e86SMelissa Wen display_e2e_pipe_params_st *pipes, 47*269c1d14SYan Li enum dc_validate_mode validate_mode); 48cf689e86SMelissa Wen void dcn20_calculate_wm(struct dc *dc, 49cf689e86SMelissa Wen struct dc_state *context, 50cf689e86SMelissa Wen display_e2e_pipe_params_st *pipes, 51cf689e86SMelissa Wen int *out_pipe_cnt, 52cf689e86SMelissa Wen int *pipe_split_from, 53cf689e86SMelissa Wen int vlevel, 54*269c1d14SYan Li enum dc_validate_mode validate_mode); 55cf689e86SMelissa Wen void dcn20_cap_soc_clocks(struct _vcs_dpi_soc_bounding_box_st *bb, 56cf689e86SMelissa Wen struct pp_smu_nv_clock_table max_clocks); 57cf689e86SMelissa Wen void dcn20_update_bounding_box(struct dc *dc, 58cf689e86SMelissa Wen struct _vcs_dpi_soc_bounding_box_st *bb, 59cf689e86SMelissa Wen struct pp_smu_nv_clock_table *max_clocks, 60cf689e86SMelissa Wen unsigned int *uclk_states, 61cf689e86SMelissa Wen unsigned int num_states); 62cf689e86SMelissa Wen void dcn20_patch_bounding_box(struct dc *dc, 63cf689e86SMelissa Wen struct _vcs_dpi_soc_bounding_box_st *bb); 642091ac69SSebastian Andrzej Siewior bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, 65*269c1d14SYan Li enum dc_validate_mode validate_mode, display_e2e_pipe_params_st *pipes); 66cf689e86SMelissa Wen void dcn20_fpu_set_wm_ranges(int i, 67cf689e86SMelissa Wen struct pp_smu_wm_range_sets *ranges, 68cf689e86SMelissa Wen struct _vcs_dpi_soc_bounding_box_st *loaded_bb); 69cf689e86SMelissa Wen void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v, 70cf689e86SMelissa Wen int vlevel, 71cf689e86SMelissa Wen int max_mpc_comb, 72cf689e86SMelissa Wen int pipe_idx, 73cf689e86SMelissa Wen bool is_validating_bw); 74cf689e86SMelissa Wen 7522f87d99SMelissa Wen int dcn21_populate_dml_pipes_from_context(struct dc *dc, 7622f87d99SMelissa Wen struct dc_state *context, 7722f87d99SMelissa Wen display_e2e_pipe_params_st *pipes, 78*269c1d14SYan Li enum dc_validate_mode validate_mode); 79*269c1d14SYan Li bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, enum 80*269c1d14SYan Li dc_validate_mode, display_e2e_pipe_params_st *pipes); 8122f87d99SMelissa Wen void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); 8222f87d99SMelissa Wen 831a340825SMelissa Wen void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params); 841a340825SMelissa Wen 856a7379f1SRodrigo Siqueira void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc, 866a7379f1SRodrigo Siqueira struct resource_context *res_ctx, 876a7379f1SRodrigo Siqueira display_e2e_pipe_params_st *pipes); 886a7379f1SRodrigo Siqueira 89ee373411SQingqing Zhuo #endif /* __DCN20_FPU_H__ */ 90