| /linux/arch/alpha/lib/ |
| H A D | fpreg.c | 15 #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val)); argument
17 #define STT(reg,val) asm volatile ("stt $f"#reg",%0" : "=m"(val)); argument
23 unsigned long val; in alpha_read_fp_reg() local
29 val = current_thread_info()->fp[reg]; in alpha_read_fp_reg()
31 case 0: STT( 0, val); break; in alpha_read_fp_reg()
32 case 1: STT( 1, val); break; in alpha_read_fp_reg()
33 case 2: STT( 2, val); break; in alpha_read_fp_reg()
34 case 3: STT( 3, val); break; in alpha_read_fp_reg()
35 case 4: STT( 4, val); break; in alpha_read_fp_reg()
36 case 5: STT( 5, val); break; in alpha_read_fp_reg()
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| /linux/drivers/media/tuners/ |
| H A D | tda18271-maps.c | 19 u8 val; member
190 { .rfmax = 62000, .val = 0x00 },
191 { .rfmax = 84000, .val = 0x01 },
192 { .rfmax = 100000, .val = 0x02 },
193 { .rfmax = 140000, .val = 0x03 },
194 { .rfmax = 170000, .val = 0x04 },
195 { .rfmax = 180000, .val = 0x05 },
196 { .rfmax = 865000, .val = 0x06 },
197 { .rfmax = 0, .val = 0x00 }, /* end */
201 { .rfmax = 61100, .val = 0x74 },
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| /linux/drivers/accel/rocket/ |
| H A D | rocket_registers.h | 23 static inline uint32_t PC_VERSION_VERSION(uint32_t val) in PC_VERSION_VERSION() argument
25 return ((val) << PC_VERSION_VERSION__SHIFT) & PC_VERSION_VERSION__MASK; in PC_VERSION_VERSION()
31 static inline uint32_t PC_VERSION_NUM_VERSION_NUM(uint32_t val) in PC_VERSION_NUM_VERSION_NUM() argument
33 return ((val) << PC_VERSION_NUM_VERSION_NUM__SHIFT) & PC_VERSION_NUM_VERSION_NUM__MASK; in PC_VERSION_NUM_VERSION_NUM()
39 static inline uint32_t PC_OPERATION_ENABLE_RESERVED_0(uint32_t val) in PC_OPERATION_ENABLE_RESERVED_0() argument
41 return ((val) << PC_OPERATION_ENABLE_RESERVED_0__SHIFT) & PC_OPERATION_ENABLE_RESERVED_0__MASK; in PC_OPERATION_ENABLE_RESERVED_0()
45 static inline uint32_t PC_OPERATION_ENABLE_OP_EN(uint32_t val) in PC_OPERATION_ENABLE_OP_EN() argument
47 return ((val) << PC_OPERATION_ENABLE_OP_EN__SHIFT) & PC_OPERATION_ENABLE_OP_EN__MASK; in PC_OPERATION_ENABLE_OP_EN()
53 static inline uint32_t PC_BASE_ADDRESS_PC_SOURCE_ADDR(uint32_t val) in PC_BASE_ADDRESS_PC_SOURCE_ADDR() argument
55 return ((val) << PC_BASE_ADDRESS_PC_SOURCE_ADDR__SHIFT) & PC_BASE_ADDRESS_PC_SOURCE_ADDR__MASK; in PC_BASE_ADDRESS_PC_SOURCE_ADDR()
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| /linux/drivers/hwtracing/coresight/ |
| H A D | coresight-etm-cp14.c | 15 int etm_readl_cp14(u32 reg, unsigned int *val) in etm_readl_cp14() argument
19 *val = etm_read(ETMCR); in etm_readl_cp14()
22 *val = etm_read(ETMCCR); in etm_readl_cp14()
25 *val = etm_read(ETMTRIGGER); in etm_readl_cp14()
28 *val = etm_read(ETMSR); in etm_readl_cp14()
31 *val = etm_read(ETMSCR); in etm_readl_cp14()
34 *val = etm_read(ETMTSSCR); in etm_readl_cp14()
37 *val = etm_read(ETMTEEVR); in etm_readl_cp14()
40 *val = etm_read(ETMTECR1); in etm_readl_cp14()
43 *val = etm_read(ETMFFLR); in etm_readl_cp14()
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| H A D | coresight-etm4x.h | 244 #define WRITE_ETM4x_REG(val, reg) \ argument
245 write_sysreg_s(val, ETM4x_REG_NUM_TO_SYSREG((reg)))
250 #define write_etm4x_sysreg_const_offset(val, offset) \ argument
251 WRITE_ETM4x_REG(val, ETM4x_OFFSET_TO_REG(offset))
256 #define CASE_WRITE(val, x) \ argument
257 case (x): { write_etm4x_sysreg_const_offset((val), (x)); break; }
262 #define ETE_ONLY_SYSREG_LIST(op, val) \ argument
263 CASE_##op((val), TRCRSR) \
264 CASE_##op((val), TRCEXTINSELRn(1)) \
265 CASE_##op((val), TRCEXTINSELRn(2)) \
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| /linux/arch/arm/include/asm/hardware/ |
| H A D | cp14.h | 12 #define dbg_write(val, reg) WCP14_##reg(val) argument
14 #define etm_write(val, reg) WCP14_##reg(val) argument
19 u32 val; \
20 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
21 val; \
24 #define MCR14(val, op1, crn, crm, op2) \ argument
26 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
152 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0) argument
153 #define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0) argument
154 #define WCP14_DBGVCR(val) MCR14(val, 0, c0, c7, 0) argument
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| /linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| H A D | types.h | 133 #define CONF_HAS(config, val) ((config) & (1 << (val))) argument
138 #define CONF_IS(config, val) ((config) == (1 << (val))) argument
139 #define CONF_GE(config, val) ((config) & (0-(1 << (val)))) argument
140 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val)))) argument
141 #define CONF_LT(config, val) ((config) & ((1 << (val))-1)) argument
142 #define CONF_LE(config, val) ((config) & (2*(1 << (val))-1)) argument
146 #define NCONF_HAS(val) CONF_HAS(NCONF, val) argument
148 #define NCONF_IS(val) CONF_IS(NCONF, val) argument
149 #define NCONF_GE(val) CONF_GE(NCONF, val) argument
150 #define NCONF_GT(val) CONF_GT(NCONF, val) argument
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| /linux/arch/loongarch/include/asm/ |
| H A D | kvm_csr.h | 19 : [val] "=r" (__v) \
30 : [val] "+r" (__v) \
41 : [val] "+r" (__v) \
49 #define write_gcsr_crmd(val) gcsr_write(val, LOONGARCH_CSR_CRMD) argument
51 #define write_gcsr_prmd(val) gcsr_write(val, LOONGARCH_CSR_PRMD) argument
53 #define write_gcsr_euen(val) gcsr_write(val, LOONGARCH_CSR_EUEN) argument
55 #define write_gcsr_misc(val) gcsr_write(val, LOONGARCH_CSR_MISC) argument
57 #define write_gcsr_ecfg(val) gcsr_write(val, LOONGARCH_CSR_ECFG) argument
59 #define write_gcsr_estat(val) gcsr_write(val, LOONGARCH_CSR_ESTAT) argument
61 #define write_gcsr_era(val) gcsr_write(val, LOONGARCH_CSR_ERA) argument
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| H A D | percpu.h | 41 unsigned long val, int size) \
50 : [val] "r" (val)); \
56 : [val] "r" (val)); \
63 return ret c_op val; \
71 static __always_inline unsigned long __percpu_xchg(void *ptr, unsigned long val, int size) in __percpu_xchg() argument
76 return __xchg_small((volatile void *)ptr, val, size); in __percpu_xchg()
79 return __xchg_asm("amswap.w", (volatile u32 *)ptr, (u32)val); in __percpu_xchg()
82 return __xchg_asm("amswap.d", (volatile u64 *)ptr, (u64)val); in __percpu_xchg()
114 : [val] "r"(_val), [ptr] "r"(&(_pcp)) \
128 #define _pcp_protect(operation, pcp, val) \ argument
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| /linux/drivers/accel/ivpu/ |
| H A D | ivpu_hw_ip.c | 73 u32 val = 0; in host_ss_rst_clr() local
75 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, TOP_NOC, val); in host_ss_rst_clr()
76 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, DSS_MAS, val); in host_ss_rst_clr()
77 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, MSS_MAS, val); in host_ss_rst_clr()
79 REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_CLR, val); in host_ss_rst_clr()
84 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); in host_ss_noc_qreqn_check_37xx() local
86 if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val)) in host_ss_noc_qreqn_check_37xx()
94 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); in host_ss_noc_qreqn_check_40xx() local
96 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val)) in host_ss_noc_qreqn_check_40xx()
112 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN); in host_ss_noc_qacceptn_check_37xx() local
[all …]
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| /linux/drivers/phy/ |
| H A D | phy-xgene.c | 555 u32 val; in sds_wr() local
565 val = readl(csr_base + indirect_cmd_reg); in sds_wr()
566 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_wr()
568 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_wr()
577 u32 val; in sds_rd() local
585 val = readl(csr_base + indirect_cmd_reg); in sds_rd()
586 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_rd()
589 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_rd()
598 u32 val; in cmu_wr() local
607 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); in cmu_wr()
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| /linux/arch/mips/include/asm/ |
| H A D | mipsregs.h | 1540 #define write_r10k_perf_cntr(counter,val) \ argument
1545 : "r" (val), "i" (counter)); \
1559 #define write_r10k_perf_cntl(counter,val) \ argument
1564 : "r" (val), "i" (counter)); \
1666 #define __write_ulong_c0_register(reg, sel, val) \ argument
1669 __write_32bit_c0_register(reg, sel, val); \
1671 __write_64bit_c0_register(reg, sel, val); \
1725 #define __write_64bit_c0_split(source, sel, val) \ argument
1727 unsigned long long __tmp = (val); \
1812 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) argument
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| /linux/tools/perf/util/ |
| H A D | expr.y | 40 double val;
76 static bool is_const(double val)
78 return isfinite(val);
84 .val = BOTTOM,
102 result.val = NAN;
104 result.val = source_count
115 result.val = BOTTOM;
131 if (!compute_ids || (is_const(LHS.val) && is_const(RHS.val))) { \
134 if (isnan(LHS.val) || isnan(RHS.val)) { \
135 RESULT.val = NAN; \
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| /linux/drivers/net/phy/ |
| H A D | phy-c45.c | 20 int val; in genphy_c45_baset1_able() local
23 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); in genphy_c45_baset1_able()
24 if (val < 0) in genphy_c45_baset1_able()
27 phydev->pma_extable = val; in genphy_c45_baset1_able()
400 int val; in genphy_c45_aneg_done() local
405 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in genphy_c45_aneg_done()
407 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0; in genphy_c45_aneg_done()
422 int val, devad; in genphy_c45_read_link() local
426 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in genphy_c45_read_link()
427 if (val < 0) in genphy_c45_read_link()
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| /linux/arch/mips/pci/ |
| H A D | pci-bcm63xx.c | 109 static void bcm63xx_int_cfg_writel(u32 val, u32 reg) in bcm63xx_int_cfg_writel() argument
116 bcm_mpi_writel(val, MPI_PCICFGDATA_REG); in bcm63xx_int_cfg_writel()
123 u32 val; in bcm63xx_reset_pcie() local
132 val = bcm_misc_readl(reg); in bcm63xx_reset_pcie()
133 val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; in bcm63xx_reset_pcie()
134 bcm_misc_writel(val, reg); in bcm63xx_reset_pcie()
152 u32 val; in bcm63xx_register_pcie() local
164 val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG); in bcm63xx_register_pcie()
165 val |= OPT1_RD_BE_OPT_EN; in bcm63xx_register_pcie()
166 val |= OPT1_RD_REPLY_BE_FIX_EN; in bcm63xx_register_pcie()
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| /linux/drivers/memory/ |
| H A D | renesas-xspi-if-regs.h | 20 #define XSPI_BMCFG_MWRSIZE(val) (((val) & 0xff) << 8) argument
25 #define XSPI_CMCFG0_FFMT(val) (((val) & 0x03) << 0) argument
26 #define XSPI_CMCFG0_ADDSIZE(val) (((val) & 0x03) << 2) argument
30 #define XSPI_CMCFG1_RDCMD(val) (((val) & 0xffff) << 0) argument
31 #define XSPI_CMCFG1_RDCMD_UPPER_BYTE(val) (((val) & 0xff) << 8) argument
32 #define XSPI_CMCFG1_RDLATE(val) (((val) & 0x1f) << 16) argument
36 #define XSPI_CMCFG2_WRCMD(val) (((val) & 0xffff) << 0) argument
37 #define XSPI_CMCFG2_WRCMD_UPPER(val) (((val) & 0xff) << 8) argument
38 #define XSPI_CMCFG2_WRLATE(val) (((val) & 0x1f) << 16) argument
42 #define XSPI_LIOCFG_PRTMD(val) (((val) & 0x3ff) << 0) argument
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| /linux/drivers/net/ethernet/chelsio/cxgb4/ |
| H A D | cxgb4_tc_u32_parse.h | 41 int (*val)(struct ch_filter_specification *f, __be32 val, __be32 mask); member
46 __be32 val, __be32 mask) in cxgb4_fill_ipv4_tos() argument
48 f->val.tos = (ntohl(val) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_tos()
55 __be32 val, __be32 mask) in cxgb4_fill_ipv4_frag() argument
60 frag_val = (ntohl(val) >> 13) & 0x00000007; in cxgb4_fill_ipv4_frag()
64 f->val.frag = 1; in cxgb4_fill_ipv4_frag()
67 f->val.frag = 0; in cxgb4_fill_ipv4_frag()
77 __be32 val, __be32 mask) in cxgb4_fill_ipv4_proto() argument
79 f->val.proto = (ntohl(val) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_proto()
86 __be32 val, __be32 mask) in cxgb4_fill_ipv4_src_ip() argument
[all …]
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| /linux/sound/pci/ac97/ |
| H A D | ac97_proc.c | 95 unsigned short val, tmp, ext, mext; in snd_ac97_proc_read_main() local
115 val = snd_ac97_read(ac97, AC97_INT_PAGING); in snd_ac97_proc_read_main()
126 AC97_PAGE_MASK, val & AC97_PAGE_MASK); in snd_ac97_proc_read_main()
130 val = ac97->caps; in snd_ac97_proc_read_main()
132 val & AC97_BC_DEDICATED_MIC ? " -dedicated MIC PCM IN channel-" : "", in snd_ac97_proc_read_main()
133 val & AC97_BC_RESERVED1 ? " -reserved1-" : "", in snd_ac97_proc_read_main()
134 val & AC97_BC_BASS_TREBLE ? " -bass & treble-" : "", in snd_ac97_proc_read_main()
135 val & AC97_BC_SIM_STEREO ? " -simulated stereo-" : "", in snd_ac97_proc_read_main()
136 val & AC97_BC_HEADPHONE ? " -headphone out-" : "", in snd_ac97_proc_read_main()
137 val & AC97_BC_LOUDNESS ? " -loudness-" : ""); in snd_ac97_proc_read_main()
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| /linux/lib/zstd/common/ |
| H A D | bits.h | 17 MEM_STATIC unsigned ZSTD_countTrailingZeros32_fallback(U32 val) in ZSTD_countTrailingZeros32_fallback() argument
19 assert(val != 0); in ZSTD_countTrailingZeros32_fallback()
25 return DeBruijnBytePos[((U32) ((val & -(S32) val) * 0x077CB531U)) >> 27]; in ZSTD_countTrailingZeros32_fallback()
29 MEM_STATIC unsigned ZSTD_countTrailingZeros32(U32 val) in ZSTD_countTrailingZeros32() argument
31 assert(val != 0); in ZSTD_countTrailingZeros32()
33 return (unsigned)__builtin_ctz(val); in ZSTD_countTrailingZeros32()
35 return ZSTD_countTrailingZeros32_fallback(val); in ZSTD_countTrailingZeros32()
39 MEM_STATIC unsigned ZSTD_countLeadingZeros32_fallback(U32 val) in ZSTD_countLeadingZeros32_fallback() argument
41 assert(val != 0); in ZSTD_countLeadingZeros32_fallback()
47 val |= val >> 1; in ZSTD_countLeadingZeros32_fallback()
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| /linux/drivers/net/wireless/ath/ath5k/ |
| H A D | eeprom.c | 43 u16 val; in ath5k_eeprom_bin2freq() local
50 val = (5 * bin) + 4800; in ath5k_eeprom_bin2freq()
52 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 : in ath5k_eeprom_bin2freq()
56 val = bin + 2300; in ath5k_eeprom_bin2freq()
58 val = bin + 2400; in ath5k_eeprom_bin2freq()
61 return val; in ath5k_eeprom_bin2freq()
76 u16 val; in ath5k_eeprom_init_header() local
96 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val); in ath5k_eeprom_init_header()
97 if (val) { in ath5k_eeprom_init_header()
98 eep_max = (val & AR5K_EEPROM_SIZE_UPPER_MASK) << in ath5k_eeprom_init_header()
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| /linux/drivers/gpu/drm/mcde/ |
| H A D | mcde_dsi.c | 70 u32 val; in mcde_dsi_irq() local
77 val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG); in mcde_dsi_irq()
78 if (val) in mcde_dsi_irq()
79 dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val); in mcde_dsi_irq()
80 if (val & DSI_DIRECT_CMD_STS_WRITE_COMPLETED) in mcde_dsi_irq()
82 if (val & DSI_DIRECT_CMD_STS_TE_RECEIVED) { in mcde_dsi_irq()
86 if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) in mcde_dsi_irq()
88 if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) in mcde_dsi_irq()
91 writel(val, d->regs + DSI_DIRECT_CMD_STS_CLR); in mcde_dsi_irq()
93 val = readl(d->regs + DSI_CMD_MODE_STS_FLAG); in mcde_dsi_irq()
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_fixed.h | 15 u32 val; member
18 #define FP_16_16_MAX ((uint_fixed_16_16_t){ .val = UINT_MAX })
20 static inline bool is_fixed16_zero(uint_fixed_16_16_t val) in is_fixed16_zero() argument
22 return val.val == 0; in is_fixed16_zero()
25 static inline uint_fixed_16_16_t u32_to_fixed16(u32 val) in u32_to_fixed16() argument
27 uint_fixed_16_16_t fp = { .val = val << 16 }; in u32_to_fixed16()
29 WARN_ON(val > U16_MAX); in u32_to_fixed16()
36 return DIV_ROUND_UP(fp.val, 1 << 16); in fixed16_to_u32_round_up()
41 return fp.val >> 16; in fixed16_to_u32()
47 uint_fixed_16_16_t min = { .val = min(min1.val, min2.val) }; in min_fixed16()
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| /linux/drivers/hwmon/ |
| H A D | hwmon-vid.c | 73 int vid_from_reg(int val, u8 vrm) in vid_from_reg() argument
81 val &= 0x3f; in vid_from_reg()
82 if ((val & 0x1f) == 0x1f) in vid_from_reg()
84 if ((val & 0x1f) <= 0x09 || val == 0x0a) in vid_from_reg()
85 vid = 1087500 - (val & 0x1f) * 25000; in vid_from_reg()
87 vid = 1862500 - (val & 0x1f) * 25000; in vid_from_reg()
88 if (val & 0x20) in vid_from_reg()
94 val &= 0xff; in vid_from_reg()
95 if (val < 0x02 || val > 0xb2) in vid_from_reg()
97 return (1600000 - (val - 2) * 6250 + 500) / 1000; in vid_from_reg()
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| /linux/drivers/media/platform/qcom/camss/ |
| H A D | camss-csid-gen2.c | 178 int val; in __csid_configure_rx() local
183 val = (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; in __csid_configure_rx()
184 val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; in __csid_configure_rx()
185 val |= phy->csiphy_id << CSI2_RX_CFG0_PHY_NUM_SEL; in __csid_configure_rx()
186 writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0); in __csid_configure_rx()
188 val = 1 << CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN; in __csid_configure_rx()
190 val |= 1 << CSI2_RX_CFG1_VC_MODE; in __csid_configure_rx()
191 val |= 1 << CSI2_RX_CFG1_MISR_EN; in __csid_configure_rx()
192 writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1); in __csid_configure_rx()
197 int val; in __csid_ctrl_rdi() local
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| /linux/arch/powerpc/lib/ |
| H A D | qspinlock.c | 106 static inline int decode_tail_cpu(u32 val) in decode_tail_cpu() argument
108 return (val >> _Q_TAIL_CPU_OFFSET) - 1; in decode_tail_cpu()
111 static inline int get_owner_cpu(u32 val) in get_owner_cpu() argument
113 return (val & _Q_OWNER_CPU_MASK) >> _Q_OWNER_CPU_OFFSET; in get_owner_cpu()
146 : "r" (&lock->val), "r"(tail), "r" (newval), in trylock_clean_tail()
176 : "r" (&lock->val), "r" (tail), "r"(_Q_TAIL_CPU_MASK) in publish_tail_cpu()
192 : "r" (&lock->val), "r" (_Q_MUST_Q_VAL) in set_mustq()
208 : "r" (&lock->val), "r" (_Q_MUST_Q_VAL) in clear_mustq()
230 : "r" (&lock->val), "r"(old), "r" (new) in try_set_sleepy()
236 static __always_inline void seen_sleepy_owner(struct qspinlock *lock, u32 val) in seen_sleepy_owner() argument
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