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Searched refs:ufshcd_rmwl (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/ufs/host/
H A Dufs-qcom.h226 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, UFS_PHY_SOFT_RESET, REG_UFS_CFG1); in ufs_qcom_assert_reset()
237 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, 0, REG_UFS_CFG1); in ufs_qcom_deassert_reset()
H A Dufs-qcom.c423 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1); in ufs_qcom_select_unipro_mode()
426 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); in ufs_qcom_select_unipro_mode()
564 ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL, in ufs_qcom_enable_hw_clk_gating()
1614 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, in ufs_qcom_enable_test_bus()
1616 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); in ufs_qcom_enable_test_bus()
1707 ufshcd_rmwl(host->hba, TEST_BUS_SEL, in ufs_qcom_testbus_config()
1710 ufshcd_rmwl(host->hba, mask, in ufs_qcom_testbus_config()
1833 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1); in ufs_qcom_dump_dbg_regs()
2130 ufshcd_rmwl(hba, ESI_VEC_MASK, FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1), in DEFINE_FREE()
H A Dufs-mediatek.c284 ufshcd_rmwl(hba, UFS_MASK(0x7FFF, 8), in ufs_mtk_hce_enable_notify()
2026 ufshcd_rmwl(hba, MCQ_INTR_EN_MSK, 0, REG_UFS_MMIO_OPT_CTRL_0); in ufs_mtk_config_mcq()
2037 ufshcd_rmwl(hba, MCQ_AH8, MCQ_AH8, REG_UFS_MMIO_OPT_CTRL_0); in ufs_mtk_config_mcq()
2038 ufshcd_rmwl(hba, MCQ_INTR_EN_MSK, MCQ_MULTI_INTR_EN, REG_UFS_MMIO_OPT_CTRL_0); in ufs_mtk_config_mcq()
/linux/drivers/ufs/core/
H A Dufs-mcq.c422 ufshcd_rmwl(hba, MCQ_MODE_SELECT, MCQ_MODE_SELECT, REG_UFS_MEM_CFG); in ufshcd_mcq_enable()
429 ufshcd_rmwl(hba, MCQ_MODE_SELECT, 0, REG_UFS_MEM_CFG); in ufshcd_mcq_disable()
/linux/include/ufs/
H A Dufshcd.h1303 * ufshcd_rmwl - perform read/modify/write for a controller register
1309 static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) in ufshcd_rmwl() function