Home
last modified time | relevance | path

Searched refs:topckgen (Results 1 – 25 of 50) sorted by relevance

12

/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8516.dtsi58 <&topckgen CLK_TOP_MAINPLL_D2>;
71 <&topckgen CLK_TOP_MAINPLL_D2>;
84 <&topckgen CLK_TOP_MAINPLL_D2>;
97 <&topckgen CLK_TOP_MAINPLL_D2>;
182 topckgen: topckgen@10000000 { label
183 compatible = "mediatek,mt8516-topckgen", "syscon";
218 clocks = <&topckgen CLK_TOP_CLK26M_D2>,
219 <&topckgen CLK_TOP_APXGPT>;
262 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
263 <&topckgen CLK_TOP_PMICWRAP_AP>;
[all …]
H A Dmt7622.dtsi251 clocks = <&topckgen CLK_TOP_HIF_SEL>;
260 <&topckgen CLK_TOP_AXI_SEL>;
296 topckgen: clock-controller@10210000 { label
297 compatible = "mediatek,mt7622-topckgen";
335 clocks = <&topckgen CLK_TOP_RTC>;
399 clocks = <&topckgen CLK_TOP_UART_SEL>,
410 clocks = <&topckgen CLK_TOP_UART_SEL>,
421 clocks = <&topckgen CLK_TOP_UART_SEL>,
432 clocks = <&topckgen CLK_TOP_UART_SEL>,
443 clocks = <&topckgen CLK_TOP_PWM_SEL>,
[all …]
H A Dmt7988a.dtsi18 <&topckgen CLK_TOP_XTAL>;
54 <&topckgen CLK_TOP_XTAL>;
66 <&topckgen CLK_TOP_XTAL>;
78 <&topckgen CLK_TOP_XTAL>;
90 <&topckgen CLK_TOP_XTAL>;
175 topckgen: clock-controller@1001b000 { label
176 compatible = "mediatek,mt7988-topckgen", "syscon";
291 clocks = <&topckgen CLK_TOP_UART_SEL>,
304 clocks = <&topckgen CLK_TOP_UART_SEL>,
315 clocks = <&topckgen CLK_TOP_UART_SEL>,
[all …]
H A Dmt7986a.dtsi156 topckgen: topckgen@1001b000 { label
157 compatible = "mediatek,mt7986-topckgen", "syscon";
202 clocks = <&topckgen CLK_TOP_PWM_SEL>,
242 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
255 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
257 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
258 <&topckgen CLK_TOP_UART_SEL>;
271 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
284 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
308 clocks = <&topckgen CLK_TOP_MPLL_D2>,
[all …]
H A Dmt2712e.dtsi90 <&topckgen CLK_TOP_F_MP0_PLL1>;
103 <&topckgen CLK_TOP_F_MP0_PLL1>;
116 <&topckgen CLK_TOP_F_BIG_PLL1>;
246 topckgen: syscon@10000000 { label
247 compatible = "mediatek,mt2712-topckgen", "syscon";
285 clocks = <&topckgen CLK_TOP_MM_SEL>,
286 <&topckgen CLK_TOP_MFG_SEL>,
287 <&topckgen CLK_TOP_VENC_SEL>,
288 <&topckgen CLK_TOP_JPGDEC_SEL>,
289 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
[all …]
H A Dmt8192.dtsi453 topckgen: syscon@10000000 { label
454 compatible = "mediatek,mt8192-topckgen", "syscon";
511 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
529 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>,
530 <&topckgen CLK_TOP_MFG_REF_SEL>;
572 clocks = <&topckgen CLK_TOP_DISP_SEL>,
586 clocks = <&topckgen CLK_TOP_IPE_SEL>,
599 clocks = <&topckgen CLK_TOP_IMG1_SEL>,
609 clocks = <&topckgen CLK_TOP_IMG2_SEL>,
619 clocks = <&topckgen CLK_TOP_MDP_SEL>,
[all …]
H A Dmt8186.dtsi855 topckgen: syscon@10000000 { label
856 compatible = "mediatek,mt8186-topckgen", "syscon";
907 clocks = <&topckgen CLK_TOP_MFG>;
934 clocks = <&topckgen CLK_TOP_SENINF>,
935 <&topckgen CLK_TOP_SENINF1>;
943 clocks = <&topckgen CLK_TOP_USB_TOP>,
959 clocks = <&topckgen CLK_TOP_AUDIODSP>,
960 <&topckgen CLK_TOP_ADSP_BUS>;
989 clocks = <&topckgen CLK_TOP_DISP>,
990 <&topckgen CLK_TOP_MDP>,
[all …]
H A Dmt8173.dtsi357 topckgen: clock-controller@10000000 { label
358 compatible = "mediatek,mt8173-topckgen";
467 clocks = <&topckgen CLK_TOP_MM_SEL>;
473 clocks = <&topckgen CLK_TOP_MM_SEL>,
474 <&topckgen CLK_TOP_VENC_SEL>;
480 clocks = <&topckgen CLK_TOP_MM_SEL>;
486 clocks = <&topckgen CLK_TOP_MM_SEL>;
493 clocks = <&topckgen CLK_TOP_MM_SEL>,
494 <&topckgen CLK_TOP_VENC_LT_SEL>;
542 <&topckgen CLK_TOP_RTC_SEL>;
[all …]
H A Dmt8188.dtsi959 topckgen: syscon@10000000 { label
960 compatible = "mediatek,mt8188-topckgen", "syscon";
1017 <&topckgen CLK_TOP_MFG_CORE_TMP>;
1043 clocks = <&topckgen CLK_TOP_VPP>,
1044 <&topckgen CLK_TOP_CAM>,
1045 <&topckgen CLK_TOP_CCU>,
1046 <&topckgen CLK_TOP_IMG>,
1047 <&topckgen CLK_TOP_VENC>,
1048 <&topckgen CLK_TOP_VDEC>,
1049 <&topckgen CLK_TOP_WPE_VPP>,
[all …]
H A Dmt8167.dtsi20 topckgen: topckgen@10000000 { label
21 compatible = "mediatek,mt8167-topckgen", "syscon";
51 clocks = <&topckgen CLK_TOP_SMI_MM>;
59 clocks = <&topckgen CLK_TOP_SMI_MM>,
60 <&topckgen CLK_TOP_RG_VDEC>;
67 clocks = <&topckgen CLK_TOP_SMI_MM>;
74 clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
75 <&topckgen CLK_TOP_RG_SLOW_MFG>;
H A Dmt8195.dtsi485 topckgen: syscon@10000000 { label
486 compatible = "mediatek,mt8195-topckgen", "syscon";
546 <&topckgen CLK_TOP_MFG_CORE_TMP>;
582 clocks = <&topckgen CLK_TOP_VPP>,
583 <&topckgen CLK_TOP_CAM>,
584 <&topckgen CLK_TOP_CCU>,
585 <&topckgen CLK_TOP_IMG>,
586 <&topckgen CLK_TOP_VENC>,
587 <&topckgen CLK_TOP_VDEC>,
588 <&topckgen CLK_TOP_WPE_VPP>,
[all …]
H A Dmt7981b.dtsi110 topckgen: clock-controller@1001b000 { label
111 compatible = "mediatek,mt7981-topckgen", "syscon";
207 clocks = <&topckgen CLK_TOP_CB_M_D2>,
208 <&topckgen CLK_TOP_SPI_SEL>,
221 clocks = <&topckgen CLK_TOP_CB_M_D2>,
222 <&topckgen CLK_TOP_SPI_SEL>,
235 clocks = <&topckgen CLK_TOP_CB_M_D2>,
236 <&topckgen CLK_TOP_SPI_SEL>,
278 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
364 clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
[all …]
H A Dmt8365.dtsi336 topckgen: syscon@10000000 { label
337 compatible = "mediatek,mt8365-topckgen", "syscon";
373 clocks = <&topckgen CLK_TOP_MM_SEL>,
435 clocks = <&topckgen CLK_TOP_CONN_32K>,
436 <&topckgen CLK_TOP_CONN_26M>;
444 clocks = <&topckgen CLK_TOP_MFG_SEL>;
452 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
462 clocks = <&topckgen CLK_TOP_DSP_SEL>,
463 <&topckgen CLK_TOP_DSP_26M>;
660 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
[all …]
H A Dmt8183.dtsi286 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
335 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
358 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
381 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
404 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
427 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
450 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
473 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
496 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
803 topckgen: syscon@10000000 { label
[all …]
H A Dmt6795.dtsi269 topckgen: syscon@10000000 { label
270 compatible = "mediatek,mt6795-topckgen", "syscon";
303 clocks = <&topckgen CLK_TOP_MM_SEL>;
309 clocks = <&topckgen CLK_TOP_MM_SEL>,
310 <&topckgen CLK_TOP_VENC_SEL>;
316 clocks = <&topckgen CLK_TOP_MM_SEL>;
323 clocks = <&topckgen CLK_TOP_MM_SEL>;
331 clocks = <&topckgen CLK_TOP_MM_SEL>,
332 <&topckgen CLK_TOP_MJC_SEL>;
402 clocks = <&topckgen CLK_TOP_PMICSPI_SEL>, <&clk26m>;
[all …]
H A Dmt6797.dtsi114 topckgen: topckgen@10000000 { label
115 compatible = "mediatek,mt6797-topckgen";
213 clocks = <&topckgen CLK_TOP_MUX_MFG>,
214 <&topckgen CLK_TOP_MUX_MM>,
215 <&topckgen CLK_TOP_MUX_VDEC>;
H A Dmt7622-rfb1.dts224 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
225 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
240 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
241 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi98 clocks = <&topckgen CLK_TOP_HIF_SEL>;
100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
137 topckgen: syscon@10210000 { label
138 compatible = "mediatek,mt7629-topckgen", "syscon";
215 clocks = <&topckgen CLK_TOP_UART_SEL>,
226 clocks = <&topckgen CLK_TOP_UART_SEL>,
237 clocks = <&topckgen CLK_TOP_UART_SEL>,
247 clocks = <&topckgen CLK_TOP_PWM_SEL>,
251 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
[all …]
H A Dmt2701.dtsi126 topckgen: syscon@10000000 { label
127 compatible = "mediatek,mt2701-topckgen", "syscon";
156 clocks = <&topckgen CLK_TOP_MM_SEL>,
157 <&topckgen CLK_TOP_MFG_SEL>,
158 <&topckgen CLK_TOP_ETHIF_SEL>;
342 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
343 <&topckgen CLK_TOP_SPI0_SEL>,
389 <&topckgen CLK_TOP_FLASH_SEL>;
402 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
403 <&topckgen CLK_TOP_SPI1_SEL>,
[all …]
H A Dmt7623.dtsi226 topckgen: syscon@10000000 { label
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
277 clocks = <&topckgen CLK_TOP_MM_SEL>,
278 <&topckgen CLK_TOP_MFG_SEL>,
279 <&topckgen CLK_TOP_ETHIF_SEL>;
423 clocks = <&topckgen CLK_TOP_PWM_SEL>,
487 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
488 <&topckgen CLK_TOP_SPI0_SEL>,
552 <&topckgen CLK_TOP_FLASH_SEL>;
[all …]
H A Dmt8135.dtsi127 topckgen: topckgen@10000000 { label
128 compatible = "mediatek,mt8135-topckgen";
/linux/Documentation/devicetree/bindings/sound/
H A Dmt6797-afe-pcm.txt29 <&topckgen CLK_TOP_MUX_AUDIO>,
30 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
31 <&topckgen CLK_TOP_SYSPLL3_D4>,
32 <&topckgen CLK_TOP_SYSPLL1_D4>,
/linux/drivers/clk/mediatek/
H A DMakefile5 …MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o
27 clk-mt6795-pericfg.o clk-mt6795-topckgen.o
63 obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o
67 obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
71 obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o
83 clk-mt8173-pericfg.o clk-mt8173-topckgen.o
100 obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-apmixedsys.o clk-mt8186-topckgen.o \
113 obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
139 obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o \
153 obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-topckgen.o \
/linux/Documentation/devicetree/bindings/soc/mediatek/
H A Dscpsys.txt68 <&topckgen CLK_TOP_MM_SEL>;
69 <&topckgen CLK_TOP_VENC_SEL>,
70 <&topckgen CLK_TOP_VENC_LT_SEL>;
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-afe-clk.c572 afe_priv->topckgen = syscon_regmap_lookup_by_phandle(of_node, in mt8186_init_clock()
574 if (IS_ERR(afe_priv->topckgen)) { in mt8186_init_clock()
576 __func__, PTR_ERR(afe_priv->topckgen)); in mt8186_init_clock()
577 return PTR_ERR(afe_priv->topckgen); in mt8186_init_clock()

12