Searched refs:tbl_hdr (Results 1 – 6 of 6) sorted by relevance
298 __encode_table_header_to_buf(&control->tbl_hdr, buf); in __write_table_header()390 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); in __calc_hdr_byte_sum()391 pp = (u8 *) &control->tbl_hdr; in __calc_hdr_byte_sum()418 struct ras_eeprom_table_header *hdr = &control->tbl_hdr; in ras_eeprom_correct_header_tag()441 struct ras_eeprom_table_header *hdr = &control->tbl_hdr; in ras_set_eeprom_table_version()449 struct ras_eeprom_table_header *hdr = &control->tbl_hdr; in ras_eeprom_reset_table()567 if (control->tbl_hdr.header == RAS_TABLE_HDR_BAD) { in ras_eeprom_check_safety_watermark()753 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; in ras_eeprom_update_header()754 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) { in ras_eeprom_update_header()767 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) in ras_eeprom_update_header()[all …]
90 struct ras_eeprom_table_header tbl_hdr; member
272 __encode_table_header_to_buf(&control->tbl_hdr, buf); in __write_table_header()368 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); in __calc_hdr_byte_sum()369 pp = (u8 *) &control->tbl_hdr; in __calc_hdr_byte_sum()396 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_correct_header_tag()420 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_set_eeprom_table_version()446 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_reset_table()593 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) { in amdgpu_ras_eeprom_check_err_threshold()798 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; in amdgpu_ras_eeprom_update_header()799 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) { in amdgpu_ras_eeprom_update_header()810 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) in amdgpu_ras_eeprom_update_header()[all …]
63 struct amdgpu_ras_eeprom_table_header tbl_hdr; member
1991 con->eeprom_control.tbl_hdr.version); in amdgpu_ras_sysfs_version_show()3256 if ((control->tbl_hdr.version < RAS_TABLE_VER_V3) && in amdgpu_ras_add_bad_pages()3390 if ((control->tbl_hdr.version < RAS_TABLE_VER_V3) && in amdgpu_ras_load_bad_pages()3836 control->tbl_hdr.version < RAS_TABLE_VER_V3) in amdgpu_ras_init_badpage_info()
794 struct hfi_queue_table_header *tbl_hdr; in venus_interface_queues_init() local830 tbl_hdr = hdev->ifaceq_table.kva; in venus_interface_queues_init()831 tbl_hdr->version = 0; in venus_interface_queues_init()832 tbl_hdr->size = IFACEQ_TABLE_SIZE; in venus_interface_queues_init()833 tbl_hdr->qhdr0_offset = sizeof(struct hfi_queue_table_header); in venus_interface_queues_init()834 tbl_hdr->qhdr_size = sizeof(struct hfi_queue_header); in venus_interface_queues_init()835 tbl_hdr->num_q = IFACEQ_NUM; in venus_interface_queues_init()836 tbl_hdr->num_active_q = IFACEQ_NUM; in venus_interface_queues_init()1732 struct hfi_queue_table_header *tbl_hdr; in venus_hfi_queues_reinit() local1756 tbl_hdr = hdev->ifaceq_table.kva; in venus_hfi_queues_reinit()[all …]