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Searched refs:sys_reg (Results 1 – 25 of 32) sorted by relevance

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/linux/tools/arch/arm64/include/asm/
H A Dsysreg.h39 #define sys_reg(op0, op1, crn, crm, op2) \ macro
44 #define sys_insn sys_reg
113 #define SYS_PSTATE_PAN sys_reg(3, 0, 4, 2, 3)
176 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
177 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
178 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
180 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
181 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
182 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
183 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
[all …]
H A Desr.h275 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \
287 sys_reg(3, \
/linux/arch/arm64/include/asm/
H A Dsysreg.h40 #define sys_reg(op0, op1, crn, crm, op2) \ macro
45 #define sys_insn sys_reg
115 #define SYS_PSTATE_PAN sys_reg(3, 0, 4, 2, 3)
182 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
183 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
184 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
186 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
187 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
188 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
189 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
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H A Dapple_m1_pmu.h10 #define SYS_IMP_APL_PMC0_EL1 sys_reg(3, 2, 15, 0, 0)
11 #define SYS_IMP_APL_PMC1_EL1 sys_reg(3, 2, 15, 1, 0)
12 #define SYS_IMP_APL_PMC2_EL1 sys_reg(3, 2, 15, 2, 0)
13 #define SYS_IMP_APL_PMC3_EL1 sys_reg(3, 2, 15, 3, 0)
14 #define SYS_IMP_APL_PMC4_EL1 sys_reg(3, 2, 15, 4, 0)
15 #define SYS_IMP_APL_PMC5_EL1 sys_reg(3, 2, 15, 5, 0)
16 #define SYS_IMP_APL_PMC6_EL1 sys_reg(3, 2, 15, 6, 0)
17 #define SYS_IMP_APL_PMC7_EL1 sys_reg(3, 2, 15, 7, 0)
18 #define SYS_IMP_APL_PMC8_EL1 sys_reg(3, 2, 15, 9, 0)
19 #define SYS_IMP_APL_PMC9_EL1 sys_reg(3, 2, 15, 10, 0)
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H A Darm_dsu_pmu.h18 #define CLUSTERPMCR_EL1 sys_reg(3, 0, 15, 5, 0)
19 #define CLUSTERPMCNTENSET_EL1 sys_reg(3, 0, 15, 5, 1)
20 #define CLUSTERPMCNTENCLR_EL1 sys_reg(3, 0, 15, 5, 2)
21 #define CLUSTERPMOVSSET_EL1 sys_reg(3, 0, 15, 5, 3)
22 #define CLUSTERPMOVSCLR_EL1 sys_reg(3, 0, 15, 5, 4)
23 #define CLUSTERPMSELR_EL1 sys_reg(3, 0, 15, 5, 5)
24 #define CLUSTERPMINTENSET_EL1 sys_reg(3, 0, 15, 5, 6)
25 #define CLUSTERPMINTENCLR_EL1 sys_reg(3, 0, 15, 5, 7)
26 #define CLUSTERPMCCNTR_EL1 sys_reg(3, 0, 15, 6, 0)
27 #define CLUSTERPMXEVTYPER_EL1 sys_reg(3, 0, 15, 6, 1)
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H A Desr.h293 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \
305 sys_reg(3, \
H A Dcpufeature.h381 u32 sys_reg; member
881 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);
/linux/drivers/input/misc/
H A Diqs626a.c446 struct iqs626_sys_reg sys_reg; member
463 struct iqs626_sys_reg *sys_reg = &iqs626->sys_reg; in iqs626_parse_events() local
472 thresh = sys_reg->ch_reg_ulp.thresh; in iqs626_parse_events()
473 hyst = &sys_reg->ch_reg_ulp.hyst; in iqs626_parse_events()
478 thresh = &sys_reg->tp_grp_reg.ch_reg_tp[0].thresh; in iqs626_parse_events()
479 hyst = &sys_reg->tp_grp_reg.hyst; in iqs626_parse_events()
486 thresh = sys_reg->ch_reg_gen[i].thresh; in iqs626_parse_events()
487 hyst = &sys_reg->ch_reg_gen[i].hyst; in iqs626_parse_events()
491 thresh = &sys_reg->ch_reg_hall.thresh; in iqs626_parse_events()
492 hyst = &sys_reg->ch_reg_hall.hyst; in iqs626_parse_events()
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H A Diqs269a.c321 struct iqs269_sys_reg sys_reg; member
346 if (!iqs269->sys_reg.slider_select[slider_num]) in iqs269_slider_type()
359 struct iqs269_ch_reg *ch_reg = iqs269->sys_reg.ch_reg; in iqs269_ati_mode_set()
384 struct iqs269_ch_reg *ch_reg = iqs269->sys_reg.ch_reg; in iqs269_ati_mode_get()
403 struct iqs269_ch_reg *ch_reg = iqs269->sys_reg.ch_reg; in iqs269_ati_base_set()
446 struct iqs269_ch_reg *ch_reg = iqs269->sys_reg.ch_reg; in iqs269_ati_base_get()
481 struct iqs269_ch_reg *ch_reg = iqs269->sys_reg.ch_reg; in iqs269_ati_target_set()
506 struct iqs269_ch_reg *ch_reg = iqs269->sys_reg.ch_reg; in iqs269_ati_target_get()
568 iqs269->sys_reg.active |= BIT(reg); in iqs269_parse_chan()
570 iqs269->sys_reg.reseed |= BIT(reg); in iqs269_parse_chan()
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/linux/tools/testing/selftests/kvm/arm64/
H A Daarch32_id_regs.c43 GUEST_ASSERT_REG_RAZ(sys_reg(3, 0, 0, 3, 3)); in guest_main()
47 GUEST_ASSERT_REG_RAZ(sys_reg(3, 0, 0, 3, 7)); in guest_main()
116 KVM_ARM64_SYS_REG(sys_reg(3, 0, 0, 3, 3)),
118 KVM_ARM64_SYS_REG(sys_reg(3, 0, 0, 3, 7)),
/linux/arch/arm64/kvm/
H A Demulate-nested.c677 sys_reg(3, 0, 0, 7, 7), CGT_HCR_TID3),
681 SR_RANGE_TRAP(sys_reg(3, 0, 11, 0, 0),
682 sys_reg(3, 0, 11, 15, 7), CGT_HCR_TIDCP),
683 SR_RANGE_TRAP(sys_reg(3, 1, 11, 0, 0),
684 sys_reg(3, 1, 11, 15, 7), CGT_HCR_TIDCP),
685 SR_RANGE_TRAP(sys_reg(3, 2, 11, 0, 0),
686 sys_reg(3, 2, 11, 15, 7), CGT_HCR_TIDCP),
687 SR_RANGE_TRAP(sys_reg(3, 3, 11, 0, 0),
688 sys_reg(3, 3, 11, 15, 7), CGT_HCR_TIDCP),
689 SR_RANGE_TRAP(sys_reg(3, 4, 11, 0, 0),
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H A Dsys_regs.h17 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
/linux/drivers/soc/qcom/
H A Dkryo-l2-accessors.c11 #define L2CPUSRSELR_EL1 sys_reg(3, 3, 15, 0, 6)
12 #define L2CPUSRDR_EL1 sys_reg(3, 3, 15, 0, 7)
/linux/arch/arm64/kvm/hyp/nvhe/
H A Dsys_regs.c285 if (reg >= sys_reg(3, 0, 0, 1, 0) && reg <= sys_reg(3, 0, 0, 7, 7)) in read_id_reg()
528 for (r = sys_reg(3, 0, 0, 4, 0); r <= sys_reg(3, 0, 0, 7, 7); r += sys_reg(0, 0, 0, 0, 1)) in kvm_init_pvm_id_regs()
/linux/drivers/irqchip/
H A Dirq-apple-aic.c167 #define SYS_IMP_APL_IPI_RR_LOCAL_EL1 sys_reg(3, 5, 15, 0, 0)
168 #define SYS_IMP_APL_IPI_RR_GLOBAL_EL1 sys_reg(3, 5, 15, 0, 1)
179 #define SYS_IMP_APL_IPI_SR_EL1 sys_reg(3, 5, 15, 1, 1)
183 #define SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2 sys_reg(3, 5, 15, 1, 3)
188 #define SYS_IMP_APL_IPI_CR_EL1 sys_reg(3, 5, 15, 3, 1)
191 #define SYS_IMP_APL_UPMCR0_EL1 sys_reg(3, 7, 15, 0, 4)
199 #define SYS_IMP_APL_UPMSR_EL1 sys_reg(3, 7, 15, 6, 4)
/linux/drivers/edac/
H A Da72_edac.c22 #define SYS_CPUMERRSR_EL1 sys_reg(3, 1, 15, 2, 2)
23 #define SYS_L2MERRSR_EL1 sys_reg(3, 1, 15, 2, 3)
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20-tamonten.dtsi322 vin-sm0-supply = <&sys_reg>;
323 vin-sm1-supply = <&sys_reg>;
324 vin-sm2-supply = <&sys_reg>;
332 sys_reg: sys { label
H A Dtegra20-ventana.dts387 vin-sm0-supply = <&sys_reg>;
388 vin-sm1-supply = <&sys_reg>;
389 vin-sm2-supply = <&sys_reg>;
397 sys_reg: sys { label
H A Dtegra20-paz00.dts342 vin-sm0-supply = <&sys_reg>;
343 vin-sm1-supply = <&sys_reg>;
344 vin-sm2-supply = <&sys_reg>;
352 sys_reg: sys { label
H A Dtegra20-harmony.dts329 vin-sm0-supply = <&sys_reg>;
330 vin-sm1-supply = <&sys_reg>;
331 vin-sm2-supply = <&sys_reg>;
339 sys_reg: sys { label
H A Dtegra20-seaboard.dts402 vin-sm0-supply = <&sys_reg>;
403 vin-sm1-supply = <&sys_reg>;
404 vin-sm2-supply = <&sys_reg>;
412 sys_reg: sys { label
H A Dtegra20-asus-transformer-common.dtsi589 vin-sm0-supply = <&sys_reg>;
590 vin-sm1-supply = <&sys_reg>;
591 vin-sm2-supply = <&sys_reg>;
599 sys_reg: sys { label
/linux/arch/arm/boot/dts/samsung/
H A Dexynos4.dtsi172 sys_reg: syscon@10010000 { label
221 samsung,sysreg = <&sys_reg>;
234 samsung,sysreg = <&sys_reg>;
247 samsung,sysreg = <&sys_reg>;
260 samsung,sysreg = <&sys_reg>;
711 samsung,sysreg = <&sys_reg>;
/linux/arch/arm64/kernel/
H A Dcpufeature.c163 .sys_reg = SYS_##reg, \
1011 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) in init_cpu_ftr_reg() argument
1019 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); in init_cpu_ftr_reg()
1628 return read_sanitised_ftr_reg(entry->sys_reg); in read_scoped_sysreg()
1630 return __read_sysreg_by_encoding(entry->sys_reg); in read_scoped_sysreg()
1640 regp = get_arm64_ftr_reg(entry->sys_reg); in has_user_cpuid_feature()
2223 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), in has_address_auth_cpucap()
2228 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), in has_address_auth_cpucap()
4133 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) in do_emulate_mrs() argument
4138 rc = emulate_sys_reg(sys_reg, &val); in do_emulate_mrs()
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/linux/Documentation/devicetree/bindings/regulator/
H A Dtps6586x.txt57 sys_reg: sys {

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