Home
last modified time | relevance | path

Searched refs:set_rate_and_parent (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/clk/ti/
H A Ddpll.c30 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
52 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
64 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
101 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
112 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
123 .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent,
/linux/drivers/clk/qcom/
H A Dclk-rcg2.c808 .set_rate_and_parent = clk_rcg2_set_rate_and_parent,
833 .set_rate_and_parent = clk_rcg2_set_floor_rate_and_parent,
846 .set_rate_and_parent = clk_rcg2_fm_set_rate_and_parent,
981 .set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
1039 .set_rate_and_parent = clk_byte_set_rate_and_parent,
1109 .set_rate_and_parent = clk_byte2_set_rate_and_parent,
1200 .set_rate_and_parent = clk_pixel_set_rate_and_parent,
1315 .set_rate_and_parent = clk_gfx3d_set_rate_and_parent,
1552 .set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
1564 .set_rate_and_parent = clk_rcg2_shared_set_floor_rate_and_parent,
[all …]
H A Dclk-rcg.c863 .set_rate_and_parent = clk_rcg_bypass2_set_rate_and_parent,
875 .set_rate_and_parent = clk_rcg_pixel_set_rate_and_parent,
887 .set_rate_and_parent = clk_rcg_esc_set_rate_and_parent,
911 .set_rate_and_parent = clk_dyn_rcg_set_rate_and_parent,
H A Dclk-regmap-mux-div.c227 .set_rate_and_parent = mux_div_set_rate_and_parent,
/linux/drivers/clk/tegra/
H A Dclk-tegra20-emc.c220 .set_rate_and_parent = emc_set_rate_and_parent,
/linux/drivers/clk/mmp/
H A Dclk-mix.c431 .set_rate_and_parent = mmp_clk_mix_set_rate_and_parent,
/linux/drivers/clk/
H A Dclk-composite.c311 clk_composite_ops->set_rate_and_parent = in __clk_hw_register_composite()
H A Dclk.c2427 if (core->ops->set_rate_and_parent) { in clk_change_rate()
2429 core->ops->set_rate_and_parent(core->hw, core->new_rate, in clk_change_rate()
3948 if (core->ops->set_rate_and_parent && in __clk_core_init()
H A Dclk-rp1.c1222 .set_rate_and_parent = rp1_clock_set_rate_and_parent,
/linux/Documentation/driver-api/
H A Dclk.rst90 int (*set_rate_and_parent)(struct clk_hw *hw,
/linux/drivers/clk/microchip/
H A Dclk-core.c548 .set_rate_and_parent = roclk_set_rate_and_parent,
/linux/include/linux/
H A Dclk-provider.h255 int (*set_rate_and_parent)(struct clk_hw *hw, member