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Searched refs:sdhci_writew (Results 1 – 25 of 27) sorted by relevance

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/linux/drivers/mmc/host/
H A Dsdhci-of-dwcmshc.c300 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); in dwcmshc_enable_card_clk()
442 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); in dwcmshc_phy_init()
443 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); in dwcmshc_phy_init()
444 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); in dwcmshc_phy_init()
448 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); in dwcmshc_phy_init()
454 sdhci_writew(host, val, PHY_STBPAD_CNFG_R); in dwcmshc_phy_init()
480 sdhci_writew(host, emmc_ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); in th1520_sdhci_set_phy()
514 sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); in dwcmshc_set_uhs_signaling()
521 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in dwcmshc_set_uhs_signaling()
592 sdhci_writew(host, DWCMSHC_SDHCI_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); in dwcmshc_sdhci_cqe_enable()
[all …]
H A Dsdhci-of-ma35d1.c104 sdhci_writew(host, ctl, MA35_SDHCI_MSHCCTL); in ma35_set_clock()
167 sdhci_writew(host, regs[idx], restore_data[idx].reg); in ma35_execute_tuning()
266 sdhci_writew(host, ctl, MA35_SDHCI_MBIUCTL); in ma35_probe()
278 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); in ma35_disable_card_clk()
H A Dsdhci-pci-arasan.c111 sdhci_writew(host, data, PHY_DAT_REG); in arasan_phy_write()
112 sdhci_writew(host, (PHY_WRITE | offset), PHY_ADDR_REG); in arasan_phy_write()
120 sdhci_writew(host, 0, PHY_DAT_REG); in arasan_phy_read()
121 sdhci_writew(host, offset, PHY_ADDR_REG); in arasan_phy_read()
H A Dsdhci-milbeaut.c94 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); in sdhci_milbeaut_reset()
99 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); in sdhci_milbeaut_reset()
193 sdhci_writew(host, ctl, F_SDH30_AHB_CONFIG); in sdhci_milbeaut_vendor_init()
220 sdhci_writew(host, ctl, SDHCI_CLOCK_CONTROL); in sdhci_milbeaut_init()
H A Dsdhci-pci-o2micro.c207 sdhci_writew(host, reg, O2_SD_VENDOR_SETTING); in sdhci_o2_set_tuning_mode()
340 sdhci_writew(host, scratch, O2_SD_MISC_CTRL); in sdhci_o2_execute_tuning()
352 sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL); in sdhci_o2_execute_tuning()
376 sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL); in sdhci_o2_execute_tuning()
422 sdhci_writew(host, scratch, O2_SD_MISC_CTRL); in sdhci_o2_execute_tuning()
569 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); in sdhci_o2_enable_clk()
574 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); in sdhci_o2_enable_clk()
589 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); in sdhci_pci_o2_set_clock()
672 sdhci_writew(host, scratch16, O2_SD_PCIE_SWITCH); in sdhci_pci_o2_init_sd_express()
H A Dsdhci-pci-gli.c418 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in gli_set_9750()
438 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in gli_set_9750()
613 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); in sdhci_gl9750_set_clock()
807 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); in sdhci_gl9755_set_clock()
1007 sdhci_writew(host, SDHCI_CLOCK_INT_EN, SDHCI_CLOCK_CONTROL); in sdhci_gli_enable_internal_clock()
1012 sdhci_writew(host, SDHCI_CTRL_V4_MODE, SDHCI_HOST_CONTROL2); in sdhci_gli_enable_internal_clock()
1264 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); in sdhci_gl9767_set_clock()
1447 sdhci_writew(host, value, SDHCI_CLOCK_CONTROL); in gl9767_init_sd_express()
1481 sdhci_writew(host, value, SDHCI_CLOCK_CONTROL); in gl9767_init_sd_express()
1729 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_set_gl9763e_signaling()
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H A Dsdhci-uhs2.c94 sdhci_writew(host, mask, SDHCI_UHS2_SW_RESET); in sdhci_uhs2_reset()
287 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in __sdhci_uhs2_set_ios()
449 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); in sdhci_uhs2_disable_clk()
462 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); in sdhci_uhs2_enable_clk()
572 sdhci_writew(host, data->blksz, SDHCI_UHS2_BLOCK_SIZE); in sdhci_uhs2_prepare_data()
573 sdhci_writew(host, data->blocks, SDHCI_UHS2_BLOCK_COUNT); in sdhci_uhs2_prepare_data()
606 sdhci_writew(host, mode, SDHCI_UHS2_TRANS_MODE); in sdhci_uhs2_set_transfer_mode()
630 sdhci_writew(host, mode, SDHCI_UHS2_TRANS_MODE); in sdhci_uhs2_set_transfer_mode()
684 sdhci_writew(host, cmd_reg, SDHCI_UHS2_CMD); in __sdhci_uhs2_send_command()
H A Dsdhci-sprd.c180 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); in sdhci_sprd_sd_clk_off()
189 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); in sdhci_sprd_sd_clk_on()
235 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); in _sdhci_sprd_set_clock()
295 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); in sdhci_sprd_set_clock()
374 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_sprd_set_uhs_signaling()
562 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_sprd_hs400_enhanced_strobe()
H A Dsdhci.c136 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in sdhci_do_enable_v4_mode()
348 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in sdhci_config_dma()
1101 sdhci_writew(host, in sdhci_set_block_info()
1111 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); in sdhci_set_block_info()
1112 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); in sdhci_set_block_info()
1114 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); in sdhci_set_block_info()
1445 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in sdhci_auto_cmd_select()
1471 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); in sdhci_set_transfer_mode()
1475 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | in sdhci_set_transfer_mode()
1498 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); in sdhci_set_transfer_mode()
[all …]
H A Dsdhci-of-at91.c78 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); in sdhci_at91_set_clock()
86 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); in sdhci_at91_set_clock()
97 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); in sdhci_at91_set_clock()
H A Dsdhci-s3c.c379 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); in sdhci_cmu_set_clock()
388 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); in sdhci_cmu_set_clock()
398 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); in sdhci_cmu_set_clock()
414 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); in sdhci_cmu_set_clock()
H A Dsdhci_f_sdh30.c78 sdhci_writew(host, 0xBC01, SDHCI_CLOCK_CONTROL); in sdhci_f_sdh30_reset()
175 sdhci_writew(host, ctrl, F_SDH30_AHB_CONFIG); in sdhci_f_sdh30_probe()
H A Dsdhci-pci-dwc-mshc.c70 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); in sdhci_snps_set_clock()
H A Dsdhci-pxav2.c146 sdhci_writew(host, 0, SDHCI_TRANSFER_MODE); in pxav1_request_done()
147 sdhci_writew(host, SDHCI_MAKE_CMD(MMC_GO_IDLE_STATE, SDHCI_CMD_RESP_NONE), in pxav1_request_done()
H A Dsdhci-xenon.c221 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in xenon_set_uhs_signaling()
301 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); in xenon_set_ios()
H A Dsdhci-brcmstb.c232 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); in sdhci_brcmstb_set_clock()
266 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_brcmstb_set_uhs_signaling()
H A Dsdhci.h739 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) in sdhci_writew() function
786 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) in sdhci_writew() function
H A Dsdhci-xenon-phy.c641 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); in xenon_emmc_phy_set()
665 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); in xenon_emmc_phy_set()
H A Dsdhci-tegra.c267 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); in tegra_sdhci_configure_card_clk()
1202 sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); in tegra_cqhci_writel()
1252 sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); in sdhci_tegra_cqe_enable()
1335 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); in sdhci_tegra_cqe_post_disable()
H A Dsdhci-acpi.c555 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); in amd_set_ios()
559 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); in amd_set_ios()
H A Dsdhci-st.c304 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_st_set_uhs_signaling()
H A Dsdhci-of-arasan.c421 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); in sdhci_arasan_set_clock()
426 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); in sdhci_arasan_set_clock()
1130 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); in arasan_zynqmp_dll_reset()
H A Dsdhci-of-aspeed.c249 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); in aspeed_sdhci_set_clock()
H A Dsdhci-pxav3.c297 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in pxav3_set_uhs_signaling()
H A Dsdhci-pci-core.c688 sdhci_writew(host, clk & ~SDHCI_CLOCK_CARD_EN, SDHCI_CLOCK_CONTROL); in sdhci_intel_set_clock()
1691 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); in amd_tuning_reset()
1695 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); in amd_tuning_reset()

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