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Searched refs:sdhci_readw (Results 1 – 25 of 26) sorted by relevance

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/linux/drivers/mmc/host/
H A Dsdhci.c58 sdhci_readw(host, SDHCI_HOST_VERSION)); in sdhci_dumpregs()
60 sdhci_readw(host, SDHCI_BLOCK_SIZE), in sdhci_dumpregs()
61 sdhci_readw(host, SDHCI_BLOCK_COUNT)); in sdhci_dumpregs()
64 sdhci_readw(host, SDHCI_TRANSFER_MODE)); in sdhci_dumpregs()
73 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); in sdhci_dumpregs()
81 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS), in sdhci_dumpregs()
82 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); in sdhci_dumpregs()
87 sdhci_readw(host, SDHCI_COMMAND), in sdhci_dumpregs()
96 sdhci_readw(host, SDHCI_HOST_CONTROL2)); in sdhci_dumpregs()
131 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_do_enable_v4_mode()
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H A Dsdhci-uhs2.c44 sdhci_readw(host, SDHCI_UHS2_BLOCK_SIZE), in sdhci_uhs2_dump_regs()
47 sdhci_readw(host, SDHCI_UHS2_CMD), in sdhci_uhs2_dump_regs()
48 sdhci_readw(host, SDHCI_UHS2_TRANS_MODE)); in sdhci_uhs2_dump_regs()
50 sdhci_readw(host, SDHCI_UHS2_DEV_INT_STATUS), in sdhci_uhs2_dump_regs()
55 sdhci_readw(host, SDHCI_UHS2_SW_RESET), in sdhci_uhs2_dump_regs()
56 sdhci_readw(host, SDHCI_UHS2_TIMER_CTRL)); in sdhci_uhs2_dump_regs()
100 if (read_poll_timeout_atomic(sdhci_readw, val, !(val & mask), 10, in sdhci_uhs2_reset()
278 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in __sdhci_uhs2_set_ios()
367 caps_ptr = sdhci_readw(host, SDHCI_UHS2_CAPS_PTR); in sdhci_uhs2_init()
446 u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_uhs2_disable_clk()
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H A Dsdhci-of-ma35d1.c99 ctl = sdhci_readw(host, MA35_SDHCI_MSHCCTL); in ma35_set_clock()
155 regs[idx] = sdhci_readw(host, restore_data[idx].reg); in ma35_execute_tuning()
263 ctl = sdhci_readw(host, MA35_SDHCI_MBIUCTL); in ma35_probe()
275 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in ma35_disable_card_clk()
H A Dsdhci-milbeaut.c92 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_milbeaut_reset()
105 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_milbeaut_reset()
189 ctl = sdhci_readw(host, F_SDH30_AHB_CONFIG); in sdhci_milbeaut_vendor_init()
218 ctl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_milbeaut_init()
H A Dsdhci-pci-o2micro.c132 scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
159 if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS)) in sdhci_o2_get_cd()
205 reg = sdhci_readw(host, O2_SD_VENDOR_SETTING); in sdhci_o2_set_tuning_mode()
217 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in __sdhci_o2_execute_tuning()
338 scratch = sdhci_readw(host, O2_SD_MISC_CTRL); in sdhci_o2_execute_tuning()
350 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_o2_execute_tuning()
374 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_o2_execute_tuning()
420 scratch = sdhci_readw(host, O2_SD_MISC_CTRL); in sdhci_o2_execute_tuning()
670 scratch16 = sdhci_readw(host, O2_SD_PCIE_SWITCH); in sdhci_pci_o2_init_sd_express()
H A Dsdhci-of-dwcmshc.c297 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in dwcmshc_enable_card_clk()
478 emmc_ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); in th1520_sdhci_set_phy()
494 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in dwcmshc_set_uhs_signaling()
512 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); in dwcmshc_set_uhs_signaling()
996 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in th1520_sdhci_reset()
1069 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in cv18xx_sdhci_set_tap()
1262 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_eic7700_set_clock()
1291 val = sdhci_readw(host, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); in sdhci_eic7700_config_phy()
1510 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_eic7700_executing_tuning()
1865 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in dwcmshc_cqhci_init()
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H A Dsdhci-sprd.c177 u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_sprd_sd_clk_off()
187 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_sprd_sd_clk_on()
342 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_sprd_set_uhs_signaling()
559 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_sprd_hs400_enhanced_strobe()
820 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); in sdhci_sprd_probe()
H A Dsdhci-pci-gli.c416 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in gli_set_9750()
436 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in gli_set_9750()
482 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in __sdhci_execute_tuning_9750()
992 if (read_poll_timeout_atomic(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE), in sdhci_wait_clock_stable()
1005 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_gli_enable_internal_clock()
1445 value = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in gl9767_init_sd_express()
1479 value = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in gl9767_init_sd_express()
1718 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_set_gl9763e_signaling()
1879 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in gl9763e_runtime_suspend()
1895 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in gl9763e_runtime_resume()
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H A Dsdhci_f_sdh30.c77 if (sdhci_readw(host, SDHCI_CLOCK_CONTROL) == 0) in sdhci_f_sdh30_reset()
171 ctrl = sdhci_readw(host, F_SDH30_AHB_CONFIG); in sdhci_f_sdh30_probe()
H A Dsdhci-pci-dwc-mshc.c36 vendor_ptr = sdhci_readw(host, SDHCI_VENDOR_PTR_R); in sdhci_snps_set_clock()
H A Dsdhci-pci-arasan.c101 val = sdhci_readw(host, PHY_ADDR_REG); in arasan_phy_addr_poll()
125 *data = sdhci_readw(host, PHY_DAT_REG) & DATA_MASK; in arasan_phy_read()
H A Dsdhci-xenon.c40 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in xenon_enable_internal_clk()
203 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in xenon_set_uhs_signaling()
299 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); in xenon_set_ios()
H A Dsdhci-of-at91.c76 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_at91_set_clock()
89 if (read_poll_timeout(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE), in sdhci_at91_set_clock()
H A Dsdhci-acpi.c488 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); in amd_select_drive_strength()
553 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); in amd_set_ios()
557 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); in amd_set_ios()
H A Dsdhci-s3c.c386 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_cmu_set_clock()
402 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) in sdhci_cmu_set_clock()
H A Dsdhci.h763 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) in sdhci_readw() function
801 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) in sdhci_readw() function
H A Dsdhci-xenon-phy.c227 err = read_poll_timeout(sdhci_readw, reg, reg & SDHCI_CLOCK_INT_STABLE, in xenon_check_stability_internal_clk()
390 if (sdhci_readw(host, XENON_SLOT_EXT_PRESENT_STATE) & in xenon_emmc_phy_enable_dll()
H A Dsdhci-of-esdhc.c1224 command = SDHCI_GET_CMD(sdhci_readw(host, in esdhc_irq()
1227 sdhci_readw(host, SDHCI_BLOCK_COUNT) && in esdhc_irq()
1351 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); in esdhc_init()
H A Dsdhci-st.c261 u16 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_st_set_uhs_signaling()
H A Dsdhci-msm.c1353 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_msm_set_uhs_signaling()
1860 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in __sdhci_msm_set_clock()
2343 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_msm_start_signal_voltage_switch()
2372 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_msm_start_signal_voltage_switch()
H A Dsdhci-pxav3.c253 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in pxav3_set_uhs_signaling()
H A Dsdhci-pci-core.c684 u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_intel_set_clock()
1689 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); in amd_tuning_reset()
1693 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); in amd_tuning_reset()
H A Dsdhci-brcmstb.c247 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_brcmstb_set_uhs_signaling()
H A Dsdhci-of-arasan.c1128 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in arasan_zynqmp_dll_reset()
1135 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in arasan_zynqmp_dll_reset()
H A Dsdhci-tegra.c256 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in tegra_sdhci_configure_card_clk()

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