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Searched refs:mtr (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/infiniband/hw/hns/
H A Dhns_roce_mr.c452 struct hns_roce_mtr *mtr = &mr->pbl_mtr; in hns_roce_map_mr_sg() local
473 mtr->hem_cfg.region[0].offset = 0; in hns_roce_map_mr_sg()
474 mtr->hem_cfg.region[0].count = mr->npages; in hns_roce_map_mr_sg()
475 mtr->hem_cfg.region[0].hopnum = mr->pbl_hop_num; in hns_roce_map_mr_sg()
476 mtr->hem_cfg.region_count = 1; in hns_roce_map_mr_sg()
477 ret = hns_roce_mtr_map(hr_dev, mtr, mr->page_list, mr->npages); in hns_roce_map_mr_sg()
492 static int mtr_map_region(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, in mtr_map_region() argument
507 mtts = hns_roce_hem_list_find_mtt(hr_dev, &mtr->hem_list, in mtr_map_region()
568 static void mtr_free_bufs(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr) in mtr_free_bufs() argument
571 if (mtr->umem) { in mtr_free_bufs()
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H A Dhns_roce_device.h426 struct hns_roce_mtr mtr; member
447 struct hns_roce_mtr mtr; member
618 struct hns_roce_mtr mtr; member
716 struct hns_roce_mtr mtr; member
1202 static inline dma_addr_t hns_roce_get_mtr_ba(struct hns_roce_mtr *mtr) in hns_roce_get_mtr_ba() argument
1204 return mtr->hem_cfg.root_ba; in hns_roce_get_mtr_ba()
1207 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1209 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1214 struct hns_roce_mtr *mtr);
1215 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
H A Dhns_roce_cq.c193 ret = hns_roce_mtr_find(hr_dev, &hr_cq->mtr, 0, mtts, ARRAY_SIZE(mtts)); in alloc_cqc()
214 hns_roce_get_mtr_ba(&hr_cq->mtr)); in alloc_cqc()
265 ret = hns_roce_mtr_create(hr_dev, &hr_cq->mtr, &buf_attr, in alloc_cq_buf()
276 hns_roce_mtr_destroy(hr_dev, &hr_cq->mtr); in free_cq_buf()
H A Dhns_roce_srq.c181 ret = hns_roce_mtr_create(hr_dev, &idx_que->mtr, &buf_attr, in alloc_srq_idx()
204 hns_roce_mtr_destroy(hr_dev, &idx_que->mtr); in alloc_srq_idx()
215 hns_roce_mtr_destroy(hr_dev, &idx_que->mtr); in free_srq_idx()
H A Dhns_roce_hw_v2.c1050 return hns_roce_buf_offset(idx_que->mtr.kmem, in get_idx_buf()
3777 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); in get_cqe_v2()
3889 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); in hns_roce_v2_write_cqc()
3891 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); in hns_roce_v2_write_cqc()
4669 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, in config_qp_rq_buf()
4678 wqe_sge_ba = hns_roce_get_mtr_ba(&hr_qp->mtr); in config_qp_rq_buf()
4709 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); in config_qp_rq_buf()
4713 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); in config_qp_rq_buf()
4746 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->sq.offset, in config_qp_sq_buf()
4754 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, in config_qp_sq_buf()
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H A Dhns_roce_qp.c809 ret = hns_roce_mtr_create(hr_dev, &hr_qp->mtr, &buf_attr, in alloc_qp_buf()
829 hns_roce_mtr_destroy(hr_dev, &hr_qp->mtr); in free_qp_buf()
1563 return hns_roce_buf_offset(hr_qp->mtr.kmem, offset); in get_wqe()
/linux/drivers/edac/
H A Di5400_edac.c287 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 10)) argument
288 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 9)) argument
289 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 8)) ? 8 : 4) argument
290 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 6)) ? 8 : 4) argument
291 #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2) argument
292 #define MTR_DIMM_RANK(mtr) (((mtr) >> 5) & 0x1) argument
293 #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1) argument
294 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) argument
295 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) argument
296 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) argument
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H A Di7300_edac.c106 u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */ member
173 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8)) argument
174 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7)) argument
175 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4) argument
176 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4) argument
177 #define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0) argument
178 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) argument
180 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) argument
181 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) argument
182 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) argument
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H A Di5000_edac.c279 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (0x1 << 8)) argument
280 #define MTR_DRAM_WIDTH(mtr) ((((mtr) >> 6) & 0x1) ? 8 : 4) argument
281 #define MTR_DRAM_BANKS(mtr) ((((mtr) >> 5) & 0x1) ? 8 : 4) argument
282 #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2) argument
283 #define MTR_DIMM_RANK(mtr) (((mtr) >> 4) & 0x1) argument
284 #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1) argument
285 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) argument
286 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) argument
287 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) argument
288 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) argument
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H A Dsb_edac.c215 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19) argument
216 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14) argument
217 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13) argument
218 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4) argument
219 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1) argument
333 enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
699 static inline int numrank(enum type type, u32 mtr) in numrank() argument
701 int ranks = (1 << RANK_CNT_BITS(mtr)); in numrank()
709 ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr); in numrank()
716 static inline int numrow(u32 mtr) in numrow() argument
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H A Di5100_edac.c329 } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN]; member
654 if (!priv->mtr[chan][chan_rank].present) in i5100_npages()
659 priv->mtr[chan][chan_rank].numcol + in i5100_npages()
660 priv->mtr[chan][chan_rank].numrow + in i5100_npages()
661 priv->mtr[chan][chan_rank].numbank; in i5100_npages()
685 priv->mtr[i][j].present = i5100_mtr_present(w); in i5100_init_mtr()
686 priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w); in i5100_init_mtr()
687 priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w); in i5100_init_mtr()
688 priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w); in i5100_init_mtr()
689 priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w); in i5100_init_mtr()
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H A Dskx_common.c318 static int get_width(u32 mtr) in get_width() argument
320 switch (GET_BITFIELD(mtr, 8, 9)) { in get_width()
457 int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm, in skx_get_dimm_info() argument
465 ranks = numrank(mtr); in skx_get_dimm_info()
466 rows = numrow(mtr); in skx_get_dimm_info()
467 cols = imc->hbm_mc ? 6 : numcol(mtr); in skx_get_dimm_info()
498 dimm->dtype = get_width(mtr); in skx_get_dimm_info()
H A Dskx_base.c183 u32 mtr, mcmtr, amap, mcddrtcfg; in skx_get_dimm_config() local
199 0x80 + 4 * j, &mtr); in skx_get_dimm_config()
200 if (IS_DIMM_PRESENT(mtr)) { in skx_get_dimm_config()
201 ndimms += skx_get_dimm_info(mtr, mcmtr, amap, dimm, imc, i, j, cfg); in skx_get_dimm_config()
H A Di10nm_base.c1075 u32 mtr, mcddrtcfg = 0; in i10nm_get_dimm_config() local
1095 mtr = I10NM_GET_DIMMMTR(imc, i, j); in i10nm_get_dimm_config()
1097 mtr, mcddrtcfg, imc->mc, i, j); in i10nm_get_dimm_config()
1099 if (IS_DIMM_PRESENT(mtr)) in i10nm_get_dimm_config()
1100 ndimms += skx_get_dimm_info(mtr, 0, 0, dimm, in i10nm_get_dimm_config()
H A Dskx_common.h346 int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
/linux/arch/alpha/include/asm/
H A Dcore_tsunami.h36 tsunami_64 mtr; member
H A Dcore_titan.h37 titan_64 mtr; member
/linux/arch/alpha/kernel/
H A Dcore_tsunami.c397 printk("%s: CSR_MTR 0x%lx\n", __func__, TSUNAMI_cchip.mtr.csr); in tsunami_init_arch()
H A Dcore_titan.c373 printk("%s: CSR_MTR 0x%lx\n", __func__, TITAN_cchip->mtr.csr); in titan_init_arch()
/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Dhwmon.c60 MLX5_SET(mtmp_reg, mtmp_in, mtr, 1); in mlx5_hwmon_reset_max_temp()
/linux/drivers/net/ethernet/mellanox/mlxsw/
H A Dreg.h9517 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
/linux/include/linux/mlx5/
H A Dmlx5_ifc.h11733 u8 mtr[0x1]; member