| /linux/drivers/gpu/drm/mcde/ |
| H A D | mcde_display.c | 75 void mcde_display_irq(struct mcde *mcde) in mcde_display_irq() argument
81 mispp = readl(mcde->regs + MCDE_MISPP); in mcde_display_irq()
82 misovl = readl(mcde->regs + MCDE_MISOVL); in mcde_display_irq()
83 mischnl = readl(mcde->regs + MCDE_MISCHNL); in mcde_display_irq()
93 if (!mcde->dpi_output && mcde_dsi_irq(mcde->mdsi)) { in mcde_display_irq()
102 if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) { in mcde_display_irq()
103 spin_lock(&mcde->flow_lock); in mcde_display_irq()
104 if (--mcde->flow_active == 0) { in mcde_display_irq()
105 dev_dbg(mcde->dev, "TE0 IRQ\n"); in mcde_display_irq()
107 val = readl(mcde->regs + MCDE_CRA0); in mcde_display_irq()
[all …]
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| H A D | mcde_drv.c | 114 struct mcde *mcde = data; in mcde_irq() local
117 val = readl(mcde->regs + MCDE_MISERR); in mcde_irq()
119 mcde_display_irq(mcde); in mcde_irq()
122 dev_info(mcde->dev, "some error IRQ\n"); in mcde_irq()
123 writel(val, mcde->regs + MCDE_RISERR); in mcde_irq()
131 struct mcde *mcde = to_mcde(drm); in mcde_modeset_init() local
142 if (!mcde->bridge) { in mcde_modeset_init()
162 mcde->dpi_output = true; in mcde_modeset_init()
163 mcde->bridge = bridge; in mcde_modeset_init()
164 mcde->flow_mode = MCDE_DPI_FORMATTER_FLOW; in mcde_modeset_init()
[all …]
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| H A D | mcde_clk_div.c | 12 struct mcde *mcde; member
20 struct mcde *mcde = cdiv->mcde; in mcde_clk_div_enable() local
23 spin_lock(&mcde->fifo_crx1_lock); in mcde_clk_div_enable()
24 val = readl(mcde->regs + cdiv->cr); in mcde_clk_div_enable()
38 writel(val, mcde->regs + cdiv->cr); in mcde_clk_div_enable()
39 spin_unlock(&mcde->fifo_crx1_lock); in mcde_clk_div_enable()
89 struct mcde *mcde = cdiv->mcde; in mcde_clk_div_recalc_rate() local
98 if (!regulator_is_enabled(mcde->epod)) in mcde_clk_div_recalc_rate()
101 cr = readl(mcde->regs + cdiv->cr); in mcde_clk_div_recalc_rate()
142 int mcde_init_clock_divider(struct mcde *mcde) in mcde_init_clock_divider() argument
[all …]
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| H A D | mcde_drm.h | 69 struct mcde { struct
98 #define to_mcde(dev) container_of(dev, struct mcde, drm) argument
100 static inline bool mcde_flow_is_video(struct mcde *mcde) in mcde_flow_is_video() argument
102 return (mcde->flow_mode == MCDE_VIDEO_TE_FLOW || in mcde_flow_is_video()
103 mcde->flow_mode == MCDE_VIDEO_FORMATTER_FLOW); in mcde_flow_is_video()
112 void mcde_display_irq(struct mcde *mcde);
113 void mcde_display_disable_irqs(struct mcde *mcde);
116 int mcde_init_clock_divider(struct mcde *mcde);
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| /linux/Documentation/gpu/ |
| H A D | mcde.rst | 4 drm/mcde ST-Ericsson MCDE Multi-channel display engine
7 .. kernel-doc:: drivers/gpu/drm/mcde/mcde_drv.c
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| H A D | drivers.rst | 11 mcde
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| /linux/Documentation/arch/sparc/ |
| H A D | adi.rst | 16 1. Set the user mode PSTATE.mcde bit. This acts as master switch for
41 kernel sets the PSTATE.mcde bit for the task. Version tags for memory
101 the task is running with ADI enabled (PSTATE.mcde=1), and the ADI
121 the task is running with ADI enabled (PSTATE.mcde=1), and the ADI
186 unsigned long i, mcde, adi_blksz, adi_nbits;
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| /linux/arch/arm/boot/dts/st/ |
| H A D | ste-dbx5x0.dtsi | 1182 mcde@a0350000 {
1183 compatible = "ste,mcde";
1190 clock-names = "mcde", "lcd", "hdmi";
1197 compatible = "ste,mcde-dsi";
1205 compatible = "ste,mcde-dsi";
1213 compatible = "ste,mcde-dsi";
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| H A D | ste-href-stuib.dtsi | 198 mcde@a0350000 {
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| H A D | ste-href-family-pinctrl.dtsi | 72 mcde {
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| H A D | ste-href-tvk1281618-r3.dtsi | 155 mcde@a0350000 {
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| H A D | ste-href.dtsi | 253 mcde@a0350000 {
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| H A D | ste-ux500-samsung-golden.dts | 361 mcde@a0350000 {
612 mcde {
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| H A D | ste-ab8505.dtsi | 310 mcde@a0350000 {
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| H A D | ste-ux500-samsung-skomer.dts | 470 mcde@a0350000 {
515 mcde {
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| H A D | ste-href-tvk1281618-r2.dtsi | 213 mcde@a0350000 {
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| H A D | ste-ux500-samsung-kyle.dts | 479 mcde@a0350000 {
527 mcde {
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| H A D | ste-hrefv60plus.dtsi | 347 mcde {
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| H A D | ste-ab8500.dtsi | 373 mcde@a0350000 {
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| H A D | ste-ux500-samsung-codina-tmo.dts | 552 mcde@a0350000 {
768 mcde {
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| H A D | ste-ux500-samsung-gavini.dts | 593 mcde@a0350000 {
620 mcde {
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| H A D | ste-ux500-samsung-janice.dts | 683 mcde@a0350000 {
710 mcde {
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| H A D | ste-ux500-samsung-codina.dts | 656 mcde@a0350000 {
932 mcde {
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| H A D | ste-snowball.dts | 651 mcde@a0350000 {
|