Lines Matching refs:mcde
75 void mcde_display_irq(struct mcde *mcde) in mcde_display_irq() argument
81 mispp = readl(mcde->regs + MCDE_MISPP); in mcde_display_irq()
82 misovl = readl(mcde->regs + MCDE_MISOVL); in mcde_display_irq()
83 mischnl = readl(mcde->regs + MCDE_MISCHNL); in mcde_display_irq()
93 if (!mcde->dpi_output && mcde_dsi_irq(mcde->mdsi)) { in mcde_display_irq()
102 if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) { in mcde_display_irq()
103 spin_lock(&mcde->flow_lock); in mcde_display_irq()
104 if (--mcde->flow_active == 0) { in mcde_display_irq()
105 dev_dbg(mcde->dev, "TE0 IRQ\n"); in mcde_display_irq()
107 val = readl(mcde->regs + MCDE_CRA0); in mcde_display_irq()
109 writel(val, mcde->regs + MCDE_CRA0); in mcde_display_irq()
111 spin_unlock(&mcde->flow_lock); in mcde_display_irq()
117 dev_dbg(mcde->dev, "chnl A vblank IRQ\n"); in mcde_display_irq()
121 dev_dbg(mcde->dev, "chnl B vblank IRQ\n"); in mcde_display_irq()
125 dev_dbg(mcde->dev, "chnl C0 vblank IRQ\n"); in mcde_display_irq()
127 dev_dbg(mcde->dev, "chnl C1 vblank IRQ\n"); in mcde_display_irq()
129 dev_dbg(mcde->dev, "chnl C0 TE IRQ\n"); in mcde_display_irq()
131 dev_dbg(mcde->dev, "chnl C1 TE IRQ\n"); in mcde_display_irq()
132 writel(mispp, mcde->regs + MCDE_RISPP); in mcde_display_irq()
135 drm_crtc_handle_vblank(&mcde->pipe.crtc); in mcde_display_irq()
138 dev_info(mcde->dev, "some stray overlay IRQ %08x\n", misovl); in mcde_display_irq()
139 writel(misovl, mcde->regs + MCDE_RISOVL); in mcde_display_irq()
142 dev_info(mcde->dev, "some stray channel error IRQ %08x\n", in mcde_display_irq()
144 writel(mischnl, mcde->regs + MCDE_RISCHNL); in mcde_display_irq()
147 void mcde_display_disable_irqs(struct mcde *mcde) in mcde_display_disable_irqs() argument
150 writel(0, mcde->regs + MCDE_IMSCPP); in mcde_display_disable_irqs()
151 writel(0, mcde->regs + MCDE_IMSCOVL); in mcde_display_disable_irqs()
152 writel(0, mcde->regs + MCDE_IMSCCHNL); in mcde_display_disable_irqs()
155 writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP); in mcde_display_disable_irqs()
156 writel(0xFFFFFFFF, mcde->regs + MCDE_RISOVL); in mcde_display_disable_irqs()
157 writel(0xFFFFFFFF, mcde->regs + MCDE_RISCHNL); in mcde_display_disable_irqs()
197 static int mcde_configure_extsrc(struct mcde *mcde, enum mcde_extsrc src, in mcde_configure_extsrc() argument
325 dev_err(mcde->dev, "Unknown pixel format 0x%08x\n", in mcde_configure_extsrc()
329 writel(val, mcde->regs + conf); in mcde_configure_extsrc()
334 writel(val, mcde->regs + cr); in mcde_configure_extsrc()
339 static void mcde_configure_overlay(struct mcde *mcde, enum mcde_overlay ovl, in mcde_configure_overlay() argument
409 writel(val, mcde->regs + conf1); in mcde_configure_overlay()
433 dev_err(mcde->dev, "Unknown pixel format 0x%08x\n", in mcde_configure_overlay()
461 dev_dbg(mcde->dev, "pixel fetcher watermark level %d pixels\n", in mcde_configure_overlay()
464 writel(val, mcde->regs + conf2); in mcde_configure_overlay()
467 writel(mcde->stride, mcde->regs + ljinc); in mcde_configure_overlay()
469 writel(0, mcde->regs + crop); in mcde_configure_overlay()
481 writel(val, mcde->regs + cr); in mcde_configure_overlay()
488 writel(val, mcde->regs + comp); in mcde_configure_overlay()
491 static void mcde_configure_channel(struct mcde *mcde, enum mcde_channel ch, in mcde_configure_channel() argument
534 switch (mcde->flow_mode) { in mcde_configure_channel()
572 dev_err(mcde->dev, "unknown flow mode %d\n", in mcde_configure_channel()
573 mcde->flow_mode); in mcde_configure_channel()
577 writel(val, mcde->regs + sync); in mcde_configure_channel()
582 writel(val, mcde->regs + conf); in mcde_configure_channel()
590 writel(val, mcde->regs + stat); in mcde_configure_channel()
591 writel(0, mcde->regs + bgcol); in mcde_configure_channel()
597 mcde->regs + mux); in mcde_configure_channel()
601 mcde->regs + mux); in mcde_configure_channel()
609 if (mcde->dpi_output) { in mcde_configure_channel()
613 dev_info(mcde->dev, "stripwidth: %d\n", stripwidth); in mcde_configure_channel()
622 writel(val, mcde->regs + MCDE_SYNCHCONFA); in mcde_configure_channel()
625 writel(val, mcde->regs + MCDE_SYNCHCONFB); in mcde_configure_channel()
631 static void mcde_configure_fifo(struct mcde *mcde, enum mcde_fifo fifo, in mcde_configure_fifo() argument
696 writel(val, mcde->regs + ctrl); in mcde_configure_fifo()
701 writel(val, mcde->regs + cr0); in mcde_configure_fifo()
703 spin_lock(&mcde->fifo_crx1_lock); in mcde_configure_fifo()
704 val = readl(mcde->regs + cr1); in mcde_configure_fifo()
709 if (mcde->dpi_output) { in mcde_configure_fifo()
710 struct drm_connector *connector = drm_panel_bridge_connector(mcde->bridge); in mcde_configure_fifo()
715 dev_info(mcde->dev, "panel does not specify bus format, assume RGB888\n"); in mcde_configure_fifo()
735 dev_err(mcde->dev, "unknown bus format, assume RGB888\n"); in mcde_configure_fifo()
745 writel(val, mcde->regs + cr1); in mcde_configure_fifo()
746 spin_unlock(&mcde->fifo_crx1_lock); in mcde_configure_fifo()
749 static void mcde_configure_dsi_formatter(struct mcde *mcde, in mcde_configure_dsi_formatter() argument
791 dev_err(mcde->dev, "tried to configure a non-DSI formatter as DSI\n"); in mcde_configure_dsi_formatter()
800 if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) in mcde_configure_dsi_formatter()
802 switch (mcde->mdsi->format) { in mcde_configure_dsi_formatter()
812 dev_err(mcde->dev, in mcde_configure_dsi_formatter()
822 dev_err(mcde->dev, "unknown DSI format\n"); in mcde_configure_dsi_formatter()
825 writel(val, mcde->regs + conf0); in mcde_configure_dsi_formatter()
827 writel(formatter_frame, mcde->regs + frame); in mcde_configure_dsi_formatter()
828 writel(pkt_size, mcde->regs + pkt); in mcde_configure_dsi_formatter()
829 writel(0, mcde->regs + sync); in mcde_configure_dsi_formatter()
835 writel(val, mcde->regs + cmdw); in mcde_configure_dsi_formatter()
841 writel(0, mcde->regs + delay0); in mcde_configure_dsi_formatter()
842 writel(0, mcde->regs + delay1); in mcde_configure_dsi_formatter()
845 static void mcde_enable_fifo(struct mcde *mcde, enum mcde_fifo fifo) in mcde_enable_fifo() argument
858 dev_err(mcde->dev, "cannot enable FIFO %c\n", in mcde_enable_fifo()
863 spin_lock(&mcde->flow_lock); in mcde_enable_fifo()
864 val = readl(mcde->regs + cr); in mcde_enable_fifo()
866 writel(val, mcde->regs + cr); in mcde_enable_fifo()
867 mcde->flow_active++; in mcde_enable_fifo()
868 spin_unlock(&mcde->flow_lock); in mcde_enable_fifo()
871 static void mcde_disable_fifo(struct mcde *mcde, enum mcde_fifo fifo, in mcde_disable_fifo() argument
886 dev_err(mcde->dev, "cannot disable FIFO %c\n", in mcde_disable_fifo()
891 spin_lock(&mcde->flow_lock); in mcde_disable_fifo()
892 val = readl(mcde->regs + cr); in mcde_disable_fifo()
894 writel(val, mcde->regs + cr); in mcde_disable_fifo()
895 mcde->flow_active = 0; in mcde_disable_fifo()
896 spin_unlock(&mcde->flow_lock); in mcde_disable_fifo()
902 while (readl(mcde->regs + cr) & MCDE_CRX0_FLOEN) { in mcde_disable_fifo()
905 dev_err(mcde->dev, in mcde_disable_fifo()
916 static void mcde_drain_pipe(struct mcde *mcde, enum mcde_fifo fifo, in mcde_drain_pipe() argument
947 val = readl(mcde->regs + ctrl); in mcde_drain_pipe()
949 dev_err(mcde->dev, "Channel A FIFO not empty (handover)\n"); in mcde_drain_pipe()
951 mcde_enable_fifo(mcde, fifo); in mcde_drain_pipe()
953 writel(MCDE_CHNLXSYNCHSW_SW_TRIG, mcde->regs + synsw); in mcde_drain_pipe()
955 mcde_disable_fifo(mcde, fifo, true); in mcde_drain_pipe()
974 static void mcde_setup_dpi(struct mcde *mcde, const struct drm_display_mode *mode, in mcde_setup_dpi() argument
977 struct drm_connector *connector = drm_panel_bridge_connector(mcde->bridge); in mcde_setup_dpi()
990 dev_info(mcde->dev, "output on DPI LCD from channel A\n"); in mcde_setup_dpi()
992 dev_info(mcde->dev, "HSW: %d, HFP: %d, HBP: %d, VSW: %d, VFP: %d, VBP: %d\n", in mcde_setup_dpi()
1028 writel(val, mcde->regs + MCDE_CONF0); in mcde_setup_dpi()
1031 writel(0, mcde->regs + MCDE_TVCRA); in mcde_setup_dpi()
1036 writel(val, mcde->regs + MCDE_TVBL1A); in mcde_setup_dpi()
1038 writel(val, mcde->regs + MCDE_TVBL2A); in mcde_setup_dpi()
1044 writel(val, mcde->regs + MCDE_TVDVOA); in mcde_setup_dpi()
1047 writel((hbp - 1), mcde->regs + MCDE_TVTIM1A); in mcde_setup_dpi()
1052 writel(val, mcde->regs + MCDE_TVLBALWA); in mcde_setup_dpi()
1055 writel(0, mcde->regs + MCDE_TVISLA); in mcde_setup_dpi()
1056 writel(0, mcde->regs + MCDE_TVBLUA); in mcde_setup_dpi()
1068 writel(val, mcde->regs + MCDE_LCDTIM1A); in mcde_setup_dpi()
1071 static void mcde_setup_dsi(struct mcde *mcde, const struct drm_display_mode *mode, in mcde_setup_dsi() argument
1084 dev_info(mcde->dev, "output in %s mode, format %dbpp\n", in mcde_setup_dsi()
1085 (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ? in mcde_setup_dsi()
1087 mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format)); in mcde_setup_dsi()
1089 mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format) / 8; in mcde_setup_dsi()
1090 dev_info(mcde->dev, "Overlay CPP: %d bytes, DSI formatter CPP %d bytes\n", in mcde_setup_dsi()
1107 writel(val, mcde->regs + MCDE_CONF0); in mcde_setup_dsi()
1121 if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) { in mcde_setup_dsi()
1129 dev_dbg(mcde->dev, "FIFO watermark after flooring: %d bytes\n", in mcde_setup_dsi()
1131 dev_dbg(mcde->dev, "Packet divisor: %d bytes\n", pkt_div); in mcde_setup_dsi()
1136 if (!(mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO)) in mcde_setup_dsi()
1139 dev_dbg(mcde->dev, "DSI packet size: %d * %d bytes per line\n", in mcde_setup_dsi()
1141 dev_dbg(mcde->dev, "Overlay frame size: %u bytes\n", in mcde_setup_dsi()
1145 dev_dbg(mcde->dev, "Formatter frame size: %u bytes\n", formatter_frame); in mcde_setup_dsi()
1159 struct mcde *mcde = to_mcde(drm); in mcde_display_enable() local
1171 ret = regulator_enable(mcde->epod); in mcde_display_enable()
1182 mcde_display_disable_irqs(mcde); in mcde_display_enable()
1183 writel(0, mcde->regs + MCDE_IMSCERR); in mcde_display_enable()
1184 writel(0xFFFFFFFF, mcde->regs + MCDE_RISERR); in mcde_display_enable()
1186 if (mcde->dpi_output) in mcde_display_enable()
1187 mcde_setup_dpi(mcde, mode, &fifo_wtrmrk); in mcde_display_enable()
1189 mcde_setup_dsi(mcde, mode, cpp, &fifo_wtrmrk, in mcde_display_enable()
1192 mcde->stride = mode->hdisplay * cpp; in mcde_display_enable()
1194 mcde->stride); in mcde_display_enable()
1197 mcde_drain_pipe(mcde, MCDE_FIFO_A, MCDE_CHANNEL_0); in mcde_display_enable()
1206 mcde_configure_extsrc(mcde, MCDE_EXTSRC_0, format); in mcde_display_enable()
1213 mcde_configure_overlay(mcde, MCDE_OVERLAY_0, MCDE_EXTSRC_0, in mcde_display_enable()
1220 mcde_configure_channel(mcde, MCDE_CHANNEL_0, MCDE_FIFO_A, mode); in mcde_display_enable()
1222 if (mcde->dpi_output) { in mcde_display_enable()
1226 mcde_configure_fifo(mcde, MCDE_FIFO_A, MCDE_DPI_FORMATTER_0, in mcde_display_enable()
1230 lcd_freq = clk_round_rate(mcde->fifoa_clk, mode->clock * 1000); in mcde_display_enable()
1231 ret = clk_set_rate(mcde->fifoa_clk, lcd_freq); in mcde_display_enable()
1233 dev_err(mcde->dev, "failed to set LCD clock rate %lu Hz\n", in mcde_display_enable()
1235 ret = clk_prepare_enable(mcde->fifoa_clk); in mcde_display_enable()
1237 dev_err(mcde->dev, "failed to enable FIFO A DPI clock\n"); in mcde_display_enable()
1240 dev_info(mcde->dev, "LCD FIFO A clk rate %lu Hz\n", in mcde_display_enable()
1241 clk_get_rate(mcde->fifoa_clk)); in mcde_display_enable()
1244 mcde_configure_fifo(mcde, MCDE_FIFO_A, MCDE_DSI_FORMATTER_0, in mcde_display_enable()
1251 mcde_dsi_enable(mcde->bridge); in mcde_display_enable()
1254 mcde_configure_dsi_formatter(mcde, MCDE_DSI_FORMATTER_0, in mcde_display_enable()
1258 switch (mcde->flow_mode) { in mcde_display_enable()
1267 writel(val, mcde->regs + MCDE_VSCRC0); in mcde_display_enable()
1269 val = readl(mcde->regs + MCDE_CRC); in mcde_display_enable()
1271 writel(val, mcde->regs + MCDE_CRC); in mcde_display_enable()
1288 if (mcde->flow_mode != MCDE_COMMAND_ONESHOT_FLOW) { in mcde_display_enable()
1289 mcde_enable_fifo(mcde, MCDE_FIFO_A); in mcde_display_enable()
1290 dev_dbg(mcde->dev, "started MCDE video FIFO flow\n"); in mcde_display_enable()
1294 val = readl(mcde->regs + MCDE_CR); in mcde_display_enable()
1296 writel(val, mcde->regs + MCDE_CR); in mcde_display_enable()
1305 struct mcde *mcde = to_mcde(drm); in mcde_display_disable() local
1312 mcde_disable_fifo(mcde, MCDE_FIFO_A, true); in mcde_display_disable()
1314 if (mcde->dpi_output) { in mcde_display_disable()
1315 clk_disable_unprepare(mcde->fifoa_clk); in mcde_display_disable()
1318 mcde_dsi_disable(mcde->bridge); in mcde_display_disable()
1330 ret = regulator_disable(mcde->epod); in mcde_display_disable()
1339 static void mcde_start_flow(struct mcde *mcde) in mcde_start_flow() argument
1342 if (mcde->flow_mode == MCDE_COMMAND_BTA_TE_FLOW) in mcde_start_flow()
1343 mcde_dsi_te_request(mcde->mdsi); in mcde_start_flow()
1346 mcde_enable_fifo(mcde, MCDE_FIFO_A); in mcde_start_flow()
1355 if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) { in mcde_start_flow()
1358 mcde->regs + MCDE_CHNL0SYNCHSW); in mcde_start_flow()
1367 mcde_disable_fifo(mcde, MCDE_FIFO_A, true); in mcde_start_flow()
1370 dev_dbg(mcde->dev, "started MCDE FIFO flow\n"); in mcde_start_flow()
1373 static void mcde_set_extsrc(struct mcde *mcde, u32 buffer_address) in mcde_set_extsrc() argument
1376 writel(buffer_address, mcde->regs + MCDE_EXTSRCXA0); in mcde_set_extsrc()
1381 writel(buffer_address + mcde->stride, mcde->regs + MCDE_EXTSRCXA1); in mcde_set_extsrc()
1389 struct mcde *mcde = to_mcde(drm); in mcde_display_update() local
1412 dev_dbg(mcde->dev, "arm vblank event\n"); in mcde_display_update()
1415 dev_dbg(mcde->dev, "insert fake vblank event\n"); in mcde_display_update()
1428 mcde_set_extsrc(mcde, drm_fb_dma_get_gem_addr(fb, pstate, 0)); in mcde_display_update()
1429 dev_info_once(mcde->dev, "first update of display contents\n"); in mcde_display_update()
1434 if (mcde->flow_active == 0) in mcde_display_update()
1435 mcde_start_flow(mcde); in mcde_display_update()
1442 dev_info(mcde->dev, "ignored a display update\n"); in mcde_display_update()
1450 struct mcde *mcde = to_mcde(drm); in mcde_display_enable_vblank() local
1460 writel(val, mcde->regs + MCDE_IMSCPP); in mcde_display_enable_vblank()
1469 struct mcde *mcde = to_mcde(drm); in mcde_display_disable_vblank() local
1472 writel(0, mcde->regs + MCDE_IMSCPP); in mcde_display_disable_vblank()
1474 writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP); in mcde_display_disable_vblank()
1488 struct mcde *mcde = to_mcde(drm); in mcde_display_init() local
1509 ret = mcde_init_clock_divider(mcde); in mcde_display_init()
1513 ret = drm_simple_display_pipe_init(drm, &mcde->pipe, in mcde_display_init()
1517 mcde->connector); in mcde_display_init()