| /linux/drivers/gpu/host1x/ |
| H A D | dev.c | 145 { /* SE1 */ .base = 0x1ac8, .offset = 0x90, .limit = 0x90 },
146 { /* SE2 */ .base = 0x1ad0, .offset = 0x90, .limit = 0x90 },
147 { /* SE3 */ .base = 0x1ad8, .offset = 0x90, .limit = 0x90 },
148 { /* SE4 */ .base = 0x1ae0, .offset = 0x90, .limit = 0x90 },
149 { /* ISP */ .base = 0x1ae8, .offset = 0x50, .limit = 0x50 },
150 { /* VIC */ .base = 0x1af0, .offset = 0x30, .limit = 0x34 },
151 { /* NVENC */ .base = 0x1af8, .offset = 0x30, .limit = 0x34 },
152 { /* NVDEC */ .base = 0x1b00, .offset = 0x30, .limit = 0x34 },
153 { /* NVJPG */ .base = 0x1b08, .offset = 0x30, .limit = 0x34 },
154 { /* TSEC */ .base = 0x1b10, .offset = 0x30, .limit = 0x34 },
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| /linux/arch/x86/mm/ |
| H A D | amdtopology.c | 82 u64 base, limit; in amd_numa_init() local
85 limit = read_pci_config(0, nb, 1, 0x44 + i*8); in amd_numa_init()
87 nodeids[i] = nodeid = limit & 7; in amd_numa_init()
95 base, limit); in amd_numa_init()
99 if (!limit) { in amd_numa_init()
104 if ((base >> 8) & 3 || (limit >> 8) & 3) { in amd_numa_init()
106 nodeid, (base >> 8) & 3, (limit >> 8) & 3); in amd_numa_init()
115 limit >>= 16; in amd_numa_init()
116 limit++; in amd_numa_init()
117 limit <<= 24; in amd_numa_init()
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| /linux/arch/arm64/lib/ |
| H A D | memcmp.S | 22 #define limit x2 macro
36 subs limit, limit, 8
44 subs limit, limit, 8
47 ldr data1, [src1, limit]
48 ldr data2, [src2, limit]
59 subs limit, limit, 16
64 cmp limit, 96
69 add limit, limit, tmp1
80 subs limit, limit, 16
94 add src1, src1, limit
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| H A D | strncmp.S | 26 #define limit x2 macro
62 cbz limit, L(ret0)
78 subs limit, limit, #8
91 add limit, limit, 8 /* Rewind limit to before last subs. */
100 cmp limit, pos, lsr #3
110 tbz limit, #63, L(not_limit)
111 add tmp1, limit, 8
112 cbz limit, L(not_limit)
114 lsl limit, tmp1, #3 /* Bits -> bytes. */
116 lsr mask, mask, limit
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| /linux/net/netfilter/ |
| H A D | nft_limit.c | 24 struct nft_limit *limit; member
37 spin_lock_bh(&priv->limit->lock); in nft_limit_eval()
39 tokens = priv->limit->tokens + now - priv->limit->last; in nft_limit_eval()
43 priv->limit->last = now; in nft_limit_eval()
46 priv->limit->tokens = delta; in nft_limit_eval()
47 spin_unlock_bh(&priv->limit->lock); in nft_limit_eval()
50 priv->limit->tokens = tokens; in nft_limit_eval()
51 spin_unlock_bh(&priv->limit->lock); in nft_limit_eval()
113 priv->limit = kmalloc(sizeof(*priv->limit), GFP_KERNEL_ACCOUNT); in nft_limit_init()
114 if (!priv->limit) in nft_limit_init()
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| H A D | nf_conntrack_sip.c | 67 const char *limit, int *shift) in string_len() argument
71 while (dptr < limit && isalpha(*dptr)) { in string_len()
79 const char *limit, int *shift) in digits_len() argument
82 while (dptr < limit && isdigit(*dptr)) { in digits_len()
100 static int word_len(const char *dptr, const char *limit) in word_len() argument
103 while (dptr < limit && iswordc(*dptr)) { in word_len()
111 const char *limit, int *shift) in callid_len() argument
115 len = word_len(dptr, limit); in callid_len()
117 if (!len || dptr == limit || *dptr != '@') in callid_len()
122 domain_len = word_len(dptr, limit); in callid_len()
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| /linux/drivers/clk/bcm/ |
| H A D | clk-kona-setup.c | 21 u32 limit; in ccu_data_offsets_valid() local
23 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
24 limit = round_down(limit, sizeof(u32)); in ccu_data_offsets_valid()
26 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
29 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
32 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
35 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
80 u32 limit; in peri_clk_data_offsets_valid() local
87 limit = range - sizeof(u32); in peri_clk_data_offsets_valid()
88 limit = round_down(limit, sizeof(u32)); in peri_clk_data_offsets_valid()
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| /linux/lib/ |
| H A D | dynamic_queue_limits.c | 85 unsigned int inprogress, prev_inprogress, limit; in dql_completed() local
102 limit = dql->limit; in dql_completed()
103 ovlimit = POSDIFF(num_queued - dql->num_completed, limit); in dql_completed()
125 limit += POSDIFF(completed, dql->prev_num_queued) + in dql_completed()
154 slack = POSDIFF(limit + dql->prev_ovlimit, in dql_completed()
166 limit = POSDIFF(limit, dql->lowest_slack); in dql_completed()
173 limit = clamp(limit, dql->min_limit, dql->max_limit); in dql_completed()
175 if (limit != dql->limit) { in dql_completed()
176 dql->limit = limit; in dql_completed()
180 dql->adj_limit = limit + completed; in dql_completed()
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| /linux/Documentation/hwmon/ |
| H A D | ina209.rst | 44 in0_max shunt voltage max alarm limit (mV)
45 in0_min shunt voltage min alarm limit (mV)
46 in0_crit_max shunt voltage crit max alarm limit (mV)
47 in0_crit_min shunt voltage crit min alarm limit (mV)
48 in0_max_alarm shunt voltage max alarm limit exceeded
49 in0_min_alarm shunt voltage min alarm limit exceeded
50 in0_crit_max_alarm shunt voltage crit max alarm limit exceeded
51 in0_crit_min_alarm shunt voltage crit min alarm limit exceeded
57 in1_max bus voltage max alarm limit (mV)
58 in1_min bus voltage min alarm limit (mV)
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| /linux/net/sched/ |
| H A D | sch_fifo.c | 23 READ_ONCE(sch->limit))) in bfifo_enqueue()
32 if (likely(sch->q.qlen < READ_ONCE(sch->limit))) in pfifo_enqueue()
43 if (unlikely(READ_ONCE(sch->limit) == 0)) in pfifo_tail_enqueue()
46 if (likely(sch->q.qlen < READ_ONCE(sch->limit))) in pfifo_tail_enqueue()
107 u32 limit = qdisc_dev(sch)->tx_queue_len; in __fifo_init() local
110 limit *= psched_mtu(qdisc_dev(sch)); in __fifo_init()
112 WRITE_ONCE(sch->limit, limit); in __fifo_init()
119 WRITE_ONCE(sch->limit, ctl->limit); in __fifo_init()
123 bypass = sch->limit >= psched_mtu(qdisc_dev(sch)); in __fifo_init()
125 bypass = sch->limit >= 1; in __fifo_init()
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| /linux/arch/powerpc/kernel/ |
| H A D | paca.c | 27 unsigned long limit, int cpu) in alloc_paca_data() argument
45 limit, nid); in alloc_paca_data()
59 static void *__init alloc_shared_lppaca(unsigned long size, unsigned long limit, in alloc_shared_lppaca() argument
80 limit, NUMA_NO_NODE); in alloc_shared_lppaca()
121 static struct lppaca * __init new_lppaca(int cpu, unsigned long limit) in new_lppaca() argument
131 lp = alloc_shared_lppaca(LPPACA_SIZE, limit, cpu); in new_lppaca()
133 lp = alloc_paca_data(LPPACA_SIZE, 0x400, limit, cpu); in new_lppaca()
149 static struct slb_shadow * __init new_slb_shadow(int cpu, unsigned long limit) in new_slb_shadow() argument
163 s = alloc_paca_data(sizeof(*s), L1_CACHE_BYTES, limit, cpu); in new_slb_shadow()
258 u64 limit; in allocate_paca() local
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| /linux/fs/romfs/ |
| H A D | storage.c | 131 unsigned long pos, size_t limit) in romfs_blk_strnlen() argument
140 while (limit > 0) { in romfs_blk_strnlen()
142 segment = min_t(size_t, limit, ROMBSIZE - offset); in romfs_blk_strnlen()
151 limit -= segment; in romfs_blk_strnlen()
217 size_t limit; in romfs_dev_read() local
219 limit = romfs_maxsize(sb); in romfs_dev_read()
220 if (pos >= limit || buflen > limit - pos) in romfs_dev_read()
240 size_t limit; in romfs_dev_strnlen() local
242 limit = romfs_maxsize(sb); in romfs_dev_strnlen()
243 if (pos >= limit) in romfs_dev_strnlen()
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-driver-intel-xe-hwmon | 5 Description: RW. Card reactive sustained (PL1) power limit in microwatts.
9 exceeds this limit. A read value of 0 means that the PL1
10 power limit is disabled, writing 0 disables the
11 limit. Writing values > 0 and <= TDP will enable the power limit.
19 Description: RO. Card default power limit (default TDP setting).
36 Description: RW. Card sustained power limit interval (Tau in PL1/Tau) in
45 Description: RW. Package reactive sustained (PL1) power limit in microwatts.
49 exceeds this limit. A read value of 0 means that the PL1
50 power limit is disabled, writing 0 disables the
51 limit. Writing values > 0 and <= TDP will enable the power limit.
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| H A D | sysfs-driver-intel-i915-hwmon | 13 Description: RW. Card reactive sustained (PL1/Tau) power limit in microwatts.
17 exceeds this limit. A read value of 0 means that the PL1
18 power limit is disabled, writing 0 disables the
19 limit. Writing values > 0 will enable the power limit.
27 Description: RO. Card default power limit (default TDP setting).
35 Description: RW. Sustained power limit interval (Tau in PL1/Tau) in
44 Description: RW. Card reactive critical (I1) power limit in microwatts.
46 Card reactive critical (I1) power limit in microwatts is exposed
49 this limit.
57 Description: RW. Card reactive critical (I1) power limit in milliamperes.
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dpll.c | 582 const struct intel_limit *limit, in intel_pll_is_valid() argument
585 if (clock->n < limit->n.min || limit->n.max < clock->n) in intel_pll_is_valid()
587 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) in intel_pll_is_valid()
589 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in intel_pll_is_valid()
591 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) in intel_pll_is_valid()
602 if (clock->p < limit->p.min || limit->p.max < clock->p) in intel_pll_is_valid()
604 if (clock->m < limit->m.min || limit->m.max < clock->m) in intel_pll_is_valid()
608 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) in intel_pll_is_valid()
613 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) in intel_pll_is_valid()
620 i9xx_select_p2_div(const struct intel_limit *limit, in i9xx_select_p2_div() argument
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| /linux/fs/xfs/ |
| H A D | xfs_qm_bhv.c | 26 uint64_t limit; in xfs_fill_statvfs_from_dquot() local
32 limit = blkres->softlimit ? in xfs_fill_statvfs_from_dquot()
35 if (limit) { in xfs_fill_statvfs_from_dquot()
38 if (limit > blkres->reserved) in xfs_fill_statvfs_from_dquot()
39 remaining = limit - blkres->reserved; in xfs_fill_statvfs_from_dquot()
41 statp->f_blocks = min(statp->f_blocks, limit); in xfs_fill_statvfs_from_dquot()
45 limit = dqp->q_ino.softlimit ? in xfs_fill_statvfs_from_dquot()
48 if (limit) { in xfs_fill_statvfs_from_dquot()
51 if (limit > dqp->q_ino.reserved) in xfs_fill_statvfs_from_dquot()
52 remaining = limit - dqp->q_ino.reserved; in xfs_fill_statvfs_from_dquot()
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | kv_smc.c | 75 u32 smc_address, u32 limit) in kv_set_smc_sram_address() argument
79 if ((smc_address + 3) > limit) in kv_set_smc_sram_address()
89 u32 *value, u32 limit) in kv_read_smc_sram_dword() argument
93 ret = kv_set_smc_sram_address(rdev, smc_address, limit); in kv_read_smc_sram_dword()
119 const u8 *src, u32 byte_count, u32 limit) in kv_copy_bytes_to_smc() argument
124 if ((smc_start_address + byte_count) > limit) in kv_copy_bytes_to_smc()
134 ret = kv_set_smc_sram_address(rdev, addr, limit); in kv_copy_bytes_to_smc()
160 ret = kv_set_smc_sram_address(rdev, addr, limit); in kv_copy_bytes_to_smc()
173 ret = kv_set_smc_sram_address(rdev, addr, limit); in kv_copy_bytes_to_smc()
188 ret = kv_set_smc_sram_address(rdev, addr, limit); in kv_copy_bytes_to_smc()
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| H A D | rv770_smc.c | 266 u16 smc_address, u16 limit) in rv770_set_smc_sram_address() argument
272 if ((smc_address + 3) > limit) in rv770_set_smc_sram_address()
285 u16 byte_count, u16 limit) in rv770_copy_bytes_to_smc() argument
294 if ((smc_start_address + byte_count) > limit) in rv770_copy_bytes_to_smc()
304 ret = rv770_set_smc_sram_address(rdev, addr, limit); in rv770_copy_bytes_to_smc()
319 ret = rv770_set_smc_sram_address(rdev, addr, limit); in rv770_copy_bytes_to_smc()
337 ret = rv770_set_smc_sram_address(rdev, addr, limit); in rv770_copy_bytes_to_smc()
455 static void rv770_clear_smc_sram(struct radeon_device *rdev, u16 limit) in rv770_clear_smc_sram() argument
461 for (i = 0; i < limit; i += 4) { in rv770_clear_smc_sram()
462 rv770_set_smc_sram_address(rdev, i, limit); in rv770_clear_smc_sram()
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| H A D | ci_smc.c | 34 u32 smc_address, u32 limit) in ci_set_smc_sram_address() argument
38 if ((smc_address + 3) > limit) in ci_set_smc_sram_address()
49 const u8 *src, u32 byte_count, u32 limit) in ci_copy_bytes_to_smc() argument
59 if ((smc_start_address + byte_count) > limit) in ci_copy_bytes_to_smc()
69 ret = ci_set_smc_sram_address(rdev, addr, limit); in ci_copy_bytes_to_smc()
84 ret = ci_set_smc_sram_address(rdev, addr, limit); in ci_copy_bytes_to_smc()
101 ret = ci_set_smc_sram_address(rdev, addr, limit); in ci_copy_bytes_to_smc()
186 int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit) in ci_load_smc_ucode() argument
247 u32 smc_address, u32 *value, u32 limit) in ci_read_smc_sram_dword() argument
253 ret = ci_set_smc_sram_address(rdev, smc_address, limit); in ci_read_smc_sram_dword()
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| /linux/drivers/gpu/drm/amd/pm/legacy-dpm/ |
| H A D | kv_smc.c | 78 u32 smc_address, u32 limit) in kv_set_smc_sram_address() argument
82 if ((smc_address + 3) > limit) in kv_set_smc_sram_address()
93 u32 *value, u32 limit) in amdgpu_kv_read_smc_sram_dword() argument
97 ret = kv_set_smc_sram_address(adev, smc_address, limit); in amdgpu_kv_read_smc_sram_dword()
123 const u8 *src, u32 byte_count, u32 limit) in amdgpu_kv_copy_bytes_to_smc() argument
128 if ((smc_start_address + byte_count) > limit) in amdgpu_kv_copy_bytes_to_smc()
138 ret = kv_set_smc_sram_address(adev, addr, limit); in amdgpu_kv_copy_bytes_to_smc()
164 ret = kv_set_smc_sram_address(adev, addr, limit); in amdgpu_kv_copy_bytes_to_smc()
177 ret = kv_set_smc_sram_address(adev, addr, limit); in amdgpu_kv_copy_bytes_to_smc()
192 ret = kv_set_smc_sram_address(adev, addr, limit); in amdgpu_kv_copy_bytes_to_smc()
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| H A D | si_smc.c | 40 u32 smc_address, u32 limit) in si_set_smc_sram_address() argument
44 if ((smc_address + 3) > limit) in si_set_smc_sram_address()
55 const u8 *src, u32 byte_count, u32 limit) in amdgpu_si_copy_bytes_to_smc() argument
63 if ((smc_start_address + byte_count) > limit) in amdgpu_si_copy_bytes_to_smc()
73 ret = si_set_smc_sram_address(adev, addr, limit); in amdgpu_si_copy_bytes_to_smc()
88 ret = si_set_smc_sram_address(adev, addr, limit); in amdgpu_si_copy_bytes_to_smc()
104 ret = si_set_smc_sram_address(adev, addr, limit); in amdgpu_si_copy_bytes_to_smc()
231 int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit) in amdgpu_si_load_smc_ucode() argument
274 u32 *value, u32 limit) in amdgpu_si_read_smc_sram_dword() argument
280 ret = si_set_smc_sram_address(adev, smc_address, limit); in amdgpu_si_read_smc_sram_dword()
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| /linux/net/wireless/ |
| H A D | of.c | 30 struct ieee80211_freq_range *limit = &freq_limits[i]; in wiphy_freq_limits_valid_chan() local
32 if (cfg80211_does_bw_fit_range(limit, in wiphy_freq_limits_valid_chan()
109 struct ieee80211_freq_range *limit = &freq_limits[i]; in wiphy_read_of_freq_limits() local
111 p = of_prop_next_u32(prop, p, &limit->start_freq_khz); in wiphy_read_of_freq_limits()
117 p = of_prop_next_u32(prop, p, &limit->end_freq_khz); in wiphy_read_of_freq_limits()
123 if (!limit->start_freq_khz || in wiphy_read_of_freq_limits()
124 !limit->end_freq_khz || in wiphy_read_of_freq_limits()
125 limit->start_freq_khz >= limit->end_freq_khz) { in wiphy_read_of_freq_limits()
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| /linux/drivers/gpu/drm/gma500/ |
| H A D | oaktrail_crtc.c | 39 static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit,
43 static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit,
86 const struct gma_limit_t *limit = NULL; in mrst_limit() local
94 limit = &mrst_limits[MRST_LIMIT_LVDS_100L]; in mrst_limit()
97 limit = &mrst_limits[MRST_LIMIT_LVDS_83]; in mrst_limit()
100 limit = &mrst_limits[MRST_LIMIT_LVDS_100]; in mrst_limit()
104 limit = &mrst_limits[MRST_LIMIT_SDVO]; in mrst_limit()
106 limit = NULL; in mrst_limit()
110 return limit; in mrst_limit()
126 static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit, in mrst_sdvo_find_best_pll() argument
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| H A D | gma_display.c | 720 const struct gma_limit_t *limit, in gma_pll_is_valid() argument
723 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) in gma_pll_is_valid()
725 if (clock->p < limit->p.min || limit->p.max < clock->p) in gma_pll_is_valid()
727 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in gma_pll_is_valid()
729 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) in gma_pll_is_valid()
734 if (clock->m < limit->m.min || limit->m.max < clock->m) in gma_pll_is_valid()
736 if (clock->n < limit->n.min || limit->n.max < clock->n) in gma_pll_is_valid()
738 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) in gma_pll_is_valid()
744 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) in gma_pll_is_valid()
750 bool gma_find_best_pll(const struct gma_limit_t *limit, in gma_find_best_pll() argument
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| /linux/kernel/cgroup/ |
| H A D | pids.c | 57 atomic64_t limit; member
87 atomic64_set(&pids->limit, PIDS_MAX); in pids_css_alloc()
172 int64_t limit = atomic64_read(&p->limit); in pids_try_charge() local
179 if (new > limit) { in pids_try_charge()
306 int64_t limit; in pids_max_write() local
311 limit = PIDS_MAX; in pids_max_write()
315 err = kstrtoll(buf, 0, &limit); in pids_max_write()
319 if (limit < 0 || limit >= PIDS_MAX) in pids_max_write()
327 atomic64_set(&pids->limit, limit); in pids_max_write()
335 int64_t limit = atomic64_read(&pids->limit); in pids_max_show() local
[all …]
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