| /linux/drivers/pinctrl/cirrus/ |
| H A D | pinctrl-cs42l43.c | 103 unsigned int group_idx) in cs42l43_pin_get_group_name() argument
105 return cs42l43_pin_groups[group_idx].name; in cs42l43_pin_get_group_name()
109 unsigned int group_idx, in cs42l43_pin_get_group_pins() argument
113 *pins = cs42l43_pin_groups[group_idx].pins; in cs42l43_pin_get_group_pins()
114 *num_pins = cs42l43_pin_groups[group_idx].npins; in cs42l43_pin_get_group_pins()
186 unsigned int func_idx, unsigned int group_idx) in cs42l43_pin_set_mux() argument
192 cs42l43_pin_groups[group_idx].name, cs42l43_pin_funcs[func_idx]); in cs42l43_pin_set_mux()
198 val = 0x2 << (group_idx + CS42L43_MIC_SHUTTER_CFG_SHIFT); in cs42l43_pin_set_mux()
203 val = 0x2 << (group_idx + CS42L43_SPK_SHUTTER_CFG_SHIFT); in cs42l43_pin_set_mux()
207 mask = BIT(group_idx + CS42L43_GPIO1_FN_SEL_SHIFT); in cs42l43_pin_set_mux()
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| H A D | pinctrl-lochnagar.c | 736 unsigned int group_idx) in lochnagar_get_group_name() argument
740 return priv->groups[group_idx].name; in lochnagar_get_group_name()
744 unsigned int group_idx, in lochnagar_get_group_pins() argument
750 *pins = priv->groups[group_idx].pins; in lochnagar_get_group_pins()
751 *num_pins = priv->groups[group_idx].npins; in lochnagar_get_group_pins()
911 unsigned int func_idx, unsigned int group_idx) in lochnagar_set_mux() argument
915 const struct lochnagar_group *group = &priv->groups[group_idx]; in lochnagar_set_mux()
989 unsigned int group_idx, bool master) in lochnagar_aif_set_master() argument
992 const struct lochnagar_group *group = &priv->groups[group_idx]; in lochnagar_aif_set_master()
1017 unsigned int group_idx, in lochnagar_conf_group_set() argument
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| /linux/scripts/gcc-plugins/ |
| H A D | randomize_layout_plugin.c | 160 unsigned long group_idx = 0; in partition_struct() local
167 if (size_groups[group_idx].tree_start == NULL_TREE) { in partition_struct()
168 size_groups[group_idx].tree_start = fields[i]; in partition_struct()
169 size_groups[group_idx].start = i; in partition_struct()
176 size_groups[group_idx].length = accum_length; in partition_struct()
178 group_idx++; in partition_struct()
182 if (size_groups[group_idx].tree_start != NULL_TREE && in partition_struct()
183 !size_groups[group_idx].length) { in partition_struct()
184 size_groups[group_idx].length = accum_length; in partition_struct()
185 group_idx++; in partition_struct()
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| /linux/drivers/pinctrl/ |
| H A D | pinctrl-k230.c | 63 unsigned int *group_idx; member
209 grp_id = func->group_idx[i]; in k230_dt_node_to_map()
222 grp_id = func->group_idx[i]; in k230_dt_node_to_map()
530 func->group_idx = devm_kcalloc(dev, func->ngroups, in k230_pinctrl_parse_functions()
531 sizeof(*func->group_idx), GFP_KERNEL); in k230_pinctrl_parse_functions()
532 if (!func->groups || !func->group_idx) in k230_pinctrl_parse_functions()
539 func->group_idx[i] = idx; in k230_pinctrl_parse_functions()
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| /linux/drivers/net/wireless/intel/iwlegacy/ |
| H A D | 3945.c | 1468 clip_pwrs = il->_3945.clip_groups[ch_info->group_idx].clip_powers; in il3945_hw_reg_set_new_power()
1574 ref_temp = (s16) eeprom->groups[ch_info->group_idx].temperature; in il3945_hw_reg_comp_txpower_temp()
1599 il->_3945.clip_groups[ch_info->group_idx].clip_powers; in il3945_hw_reg_comp_txpower_temp()
1893 u16 group_idx = 0; /* based on factory calib frequencies */ in il3945_hw_reg_get_ch_grp_idx() local
1901 group_idx = group; in il3945_hw_reg_get_ch_grp_idx()
1907 group_idx = 4; in il3945_hw_reg_get_ch_grp_idx()
1909 group_idx = 0; /* 2.4 GHz, group 0 */ in il3945_hw_reg_get_ch_grp_idx()
1911 D_POWER("Chnl %d mapped to grp %d\n", ch_info->channel, group_idx); in il3945_hw_reg_get_ch_grp_idx()
1912 return group_idx; in il3945_hw_reg_get_ch_grp_idx()
2084 ch_info->group_idx = il3945_hw_reg_get_ch_grp_idx(il, ch_info); in il3945_txpower_set_from_eeprom()
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| H A D | common.h | 484 u8 group_idx; /* 0-4, maps channel to group1/2/3/4/5 */ member
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/ |
| H A D | dcn20_optc.c | 107 int group_idx, in optc2_set_gsl_source_select() argument
112 switch (group_idx) { in optc2_set_gsl_source_select()
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| H A D | dcn20_optc.h | 98 int group_idx,
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| /linux/drivers/perf/ |
| H A D | cxl_pmu.c | 154 u8 group_idx; in cxl_pmu_parse_caps() local
168 group_idx = FIELD_GET(CXL_PMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, val); in cxl_pmu_parse_caps()
170 eval = readq(base + CXL_PMU_EVENT_CAP_REG(group_idx)); in cxl_pmu_parse_caps()
186 set_bit(group_idx, &fixed_counter_event_cap_bm); in cxl_pmu_parse_caps()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 224 int group_idx; in dcn20_setup_gsl_group_as_lock() local
235 group_idx = find_free_gsl_group(dc); in dcn20_setup_gsl_group_as_lock()
236 ASSERT(group_idx != 0); in dcn20_setup_gsl_group_as_lock()
237 pipe_ctx->stream_res.gsl_group = group_idx; in dcn20_setup_gsl_group_as_lock()
240 switch (group_idx) { in dcn20_setup_gsl_group_as_lock()
259 group_idx = pipe_ctx->stream_res.gsl_group; in dcn20_setup_gsl_group_as_lock()
260 if (group_idx == 0) in dcn20_setup_gsl_group_as_lock()
266 switch (group_idx) { in dcn20_setup_gsl_group_as_lock()
293 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); in dcn20_setup_gsl_group_as_lock()
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| /linux/net/mac80211/ |
| H A D | rc80211_minstrel_ht.c | 1445 int group_idx = MI_RATE_GROUP(index); in minstrel_ht_set_rate() local
1446 const struct mcs_group *group = &minstrel_mcs_groups[group_idx]; in minstrel_ht_set_rate()
1466 if (group_idx == MINSTREL_CCK_GROUP) in minstrel_ht_set_rate()
1468 else if (group_idx == MINSTREL_OFDM_GROUP) in minstrel_ht_set_rate()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 3359 int group_idx; in dcn401_setup_gsl_group_as_lock_sequence() local
3370 group_idx = find_free_gsl_group(dc); in dcn401_setup_gsl_group_as_lock_sequence()
3371 ASSERT(group_idx != 0); in dcn401_setup_gsl_group_as_lock_sequence()
3372 pipe_ctx->stream_res.gsl_group = group_idx; in dcn401_setup_gsl_group_as_lock_sequence()
3375 switch (group_idx) { in dcn401_setup_gsl_group_as_lock_sequence()
3394 group_idx = pipe_ctx->stream_res.gsl_group; in dcn401_setup_gsl_group_as_lock_sequence()
3395 if (group_idx == 0) in dcn401_setup_gsl_group_as_lock_sequence()
3401 switch (group_idx) { in dcn401_setup_gsl_group_as_lock_sequence()
3422 hwss_add_tg_set_gsl_source_select(seq_state, pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); in dcn401_setup_gsl_group_as_lock_sequence()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | timing_generator.h | 491 int group_idx,
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 2583 int group_idx = params->tg_set_gsl_source_select_params.group_idx; in hwss_tg_set_gsl_source_select() local
2587 tg->funcs->set_gsl_source_select(tg, group_idx, gsl_ready_signal); in hwss_tg_set_gsl_source_select()
3505 int group_idx, in hwss_add_tg_set_gsl_source_select() argument
3511 …q_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.group_idx = group_idx; in hwss_add_tg_set_gsl_source_select()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/ |
| H A D | hw_sequencer.h | 296 int group_idx; member
1811 int group_idx,
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