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Searched refs:dwbc30 (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
H A Ddcn30_dwb_cm.c37 dwbc30->dwbc_regs->reg
40 dwbc30->base.ctx
44 dwbc30->dwbc_shift->field_name, dwbc30->dwbc_mask->field_name
49 static void dwb3_get_reg_field_ogam(struct dcn30_dwbc *dwbc30, in dwb3_get_reg_field_ogam() argument
52 reg->shifts.field_region_start_base = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B; in dwb3_get_reg_field_ogam()
53 reg->masks.field_region_start_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B; in dwb3_get_reg_field_ogam()
54 reg->shifts.field_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_OFFSET_B; in dwb3_get_reg_field_ogam()
55 reg->masks.field_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_OFFSET_B; in dwb3_get_reg_field_ogam()
57 reg->shifts.exp_region0_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dwb3_get_reg_field_ogam()
58 reg->masks.exp_region0_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dwb3_get_reg_field_ogam()
[all …]
H A Ddcn30_dwb.c34 dwbc30->dwbc_regs->reg
37 dwbc30->base.ctx
41 dwbc30->dwbc_shift->field_name, dwbc30->dwbc_mask->field_name
44 dwbc30->base.ctx->logger
68 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_config_fc() local
93 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_enable() local
121 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_disable() local
135 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_set_fc_enable() local
157 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_update() local
195 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_is_enabled() local
[all …]
H A Ddcn30_dwb.h877 void dcn30_dwbc_construct(struct dcn30_dwbc *dwbc30,
/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn35/
H A Ddcn35_dwb.c28 dwbc30->dwbc_regs->reg
31 dwbc30->base.ctx
35 ((const struct dcn35_dwbc_shift *)(dwbc30->dwbc_shift))->field_name, \
36 ((const struct dcn35_dwbc_mask *)(dwbc30->dwbc_mask)) \
40 dwbc30->base.ctx->logger
42 void dcn35_dwbc_construct(struct dcn30_dwbc *dwbc30, in dcn35_dwbc_construct() argument
49 dcn30_dwbc_construct(dwbc30, ctx, dwbc_regs, in dcn35_dwbc_construct()
54 void dcn35_dwbc_set_fgcg(struct dcn30_dwbc *dwbc30, bool enable) in dcn35_dwbc_set_fgcg() argument
H A Ddcn35_dwb.h52 void dcn35_dwbc_construct(struct dcn30_dwbc *dwbc30,
59 void dcn35_dwbc_set_fgcg(struct dcn30_dwbc *dwbc30, bool enable);
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c1609 static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx) in dcn35_dwbc_init() argument
1612 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb); in dcn35_dwbc_init()
1621 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc); in dcn35_dwbc_create() local
1623 if (!dwbc30) { in dcn35_dwbc_create()
1632 dcn35_dwbc_construct(dwbc30, ctx, in dcn35_dwbc_create()
1638 pool->dwbc[i] = &dwbc30->base; in dcn35_dwbc_create()
1640 dcn35_dwbc_init(dwbc30, ctx); in dcn35_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c1616 static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx) in dcn35_dwbc_init() argument
1619 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb); in dcn35_dwbc_init()
1628 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc); in dcn35_dwbc_create() local
1630 if (!dwbc30) { in dcn35_dwbc_create()
1639 dcn35_dwbc_construct(dwbc30, ctx, in dcn35_dwbc_create()
1645 pool->dwbc[i] = &dwbc30->base; in dcn35_dwbc_create()
1647 dcn35_dwbc_init(dwbc30, ctx); in dcn35_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c1629 static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx) in dcn35_dwbc_init() argument
1632 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb); in dcn35_dwbc_init()
1641 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc); in dcn35_dwbc_create() local
1643 if (!dwbc30) { in dcn35_dwbc_create()
1652 dcn35_dwbc_construct(dwbc30, ctx, in dcn35_dwbc_create()
1658 pool->dwbc[i] = &dwbc30->base; in dcn35_dwbc_create()
1660 dcn35_dwbc_init(dwbc30, ctx); in dcn35_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c706 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc); in dcn303_dwbc_create() local
708 if (!dwbc30) { in dcn303_dwbc_create()
713 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); in dcn303_dwbc_create()
715 pool->dwbc[i] = &dwbc30->base; in dcn303_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c745 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc); in dcn302_dwbc_create() local
747 if (!dwbc30) { in dcn302_dwbc_create()
752 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); in dcn302_dwbc_create()
754 pool->dwbc[i] = &dwbc30->base; in dcn302_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c1216 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc); in dcn301_dwbc_create() local
1218 if (!dwbc30) { in dcn301_dwbc_create()
1223 dcn30_dwbc_construct(dwbc30, ctx, in dcn301_dwbc_create()
1229 pool->dwbc[i] = &dwbc30->base; in dcn301_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c1610 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc); in dcn31_dwbc_create() local
1612 if (!dwbc30) { in dcn31_dwbc_create()
1617 dcn30_dwbc_construct(dwbc30, ctx, in dcn31_dwbc_create()
1623 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c1545 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc); in dcn31_dwbc_create() local
1547 if (!dwbc30) { in dcn31_dwbc_create()
1552 dcn30_dwbc_construct(dwbc30, ctx, in dcn31_dwbc_create()
1558 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c1552 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc); in dcn31_dwbc_create() local
1554 if (!dwbc30) { in dcn31_dwbc_create()
1559 dcn30_dwbc_construct(dwbc30, ctx, in dcn31_dwbc_create()
1565 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c1526 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc); in dcn321_dwbc_create() local
1528 if (!dwbc30) { in dcn321_dwbc_create()
1537 dcn30_dwbc_construct(dwbc30, ctx, in dcn321_dwbc_create()
1543 pool->dwbc[i] = &dwbc30->base; in dcn321_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c1553 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc); in dcn31_dwbc_create() local
1555 if (!dwbc30) { in dcn31_dwbc_create()
1560 dcn30_dwbc_construct(dwbc30, ctx, in dcn31_dwbc_create()
1566 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1256 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc); in dcn30_dwbc_create() local
1258 if (!dwbc30) { in dcn30_dwbc_create()
1263 dcn30_dwbc_construct(dwbc30, ctx, in dcn30_dwbc_create()
1269 pool->dwbc[i] = &dwbc30->base; in dcn30_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c1546 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc); in dcn32_dwbc_create() local
1548 if (!dwbc30) { in dcn32_dwbc_create()
1557 dcn30_dwbc_construct(dwbc30, ctx, in dcn32_dwbc_create()
1563 pool->dwbc[i] = &dwbc30->base; in dcn32_dwbc_create()